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AD5424 Datenblatt(PDF) 4 Page - Analog Devices |
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AD5424 Datenblatt(HTML) 4 Page - Analog Devices |
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4 / 24 page ![]() REV. 0 –4– AD5424/AD5433/AD5445 t5 DATA VALID t4 t2 CS R/ W DATA t1 DATA VALID t2 t9 t8 t3 t6 t7 Figure 1. Timing Diagram TIMING CHARACTERISTICS1, 2 Parameter VDD = 2.5 V to 5.5 V VDD = 4.5 V to 5.5 V Unit Conditions/Comments t1 00 ns min R/ W to CS setup time t2 00 ns min R/ W to CS hold time t3 10 10 ns min CS low time (write cycle) t4 66 ns min Data setup time t5 00 ns min Data hold time t6 55 ns min R/ W high to CS low t7 97 ns min CS min high time t8 20 10 ns typ Data access time 40 20 ns max t9 55 ns typ Bus relinquish time 10 10 ns max NOTES 1See Figure 1. Temperature range is as follows: Y version: –40 C to +125 C. Guaranteed by design and characterization, not subject to production test. 2All input signals are specified with tr = tf = 1 ns (10% to 90% of V DD) and timed from a voltage level of (V IL + VIH)/2. Digital output timing measured with load circuit in Figure 2. Specifications subject to change without notice. (VREF = 5 V, IOUT2 = O V. All specifications TMIN to TMAX, unless otherwise noted.) |
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