ADF41513

Preliminary Technical Data

Rev. PrL | Page 18 of 33

REGISTER 1 (R1) MAP

DITHER2

Set Register 1, Bit 31 = 1 to enable the Σ-Δ modulator dither.

Enabling DITHER2 can reduce fractional spurs.

FRAC1

Register 1, Bits[28:4] set the FRAC1 value. See the N Divider

and R Counter section for more information. When using a

fixed modulus, Bits [28:4] are the FRAC value.

FRAC1 REGISTER (R1)

DBB

DB31

CONTROL

BITS

25-BIT FRAC1 VALUE (FRAC1)

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7 DB6

DB5 DB4

DB3 DB2

DB1 DB0

0

0

D1

F1

F2

F3

F4

F5

F6

F8

F7

F9

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

F25

C3(0)

C4(0)

C2(0) C1(1)

NOTES

1. DBB = DOUBLE-BUFFERED BITS.

F25

F24

...

F2

F1

FRAC1 WORD

0

0

...

0

0

0

0

0

...

0

1

1

0

0

...

1

0

2

0

0

...

1

1

3

.

.

...

.

.

.

.

.

...

.

.

.

.

.

...

.

.

.

1

1

...

0

0

33,554,428

1

1

...

0

1

33,554,429

1

1

...

1

0

33,554,430

1

1

...

1

1

33,554,431

D1

DITHER2

0

OFF

1

ON

Figure 22. Register 1 (R1) Map