ADF41513 datasheet(24/33 Pages) AD

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ADF41513

Preliminary Technical Data

Rev. PrL | Page 24 of 33

Bleed Current

current is set by

Bleed Current (µA) = (1.8 ×10−9 + (7/fRF)) × (ICP × fPFD) × 106

(6)

where:

fRF is the RF signal frequency in Hz.

ICP is the charge pump current in A.

fPFD is the PFD frequency in Hz.

Bleed Polarity

Negative polarity is the typical usage.

Bleed Enable

In fractional mode of operation, charge pump linearity and,

ultimately, phase noise and spurious performance, is much

better if the VCO and reference inputs to the phase detector

operate with a phase offset. This phase offset is implemented by

adding a constant bleed current at the output of the charge

pump. Use bleed only when operating in fractional-N mode,

that is FRAC1 or FRAC2 not equal to 0. Set Register 6, Bit 22 =

1 to enable bleed.

INT Mode

modulator (SDM). Setting Register 6, Bit 20 = 1 disables the

SDM so the ADF41513 operates purely in integer N mode.

Disabling the SDM improves phase noise performance and

changes the frequency resolution to fPFD.

ABP

Recommended setting for best figure of merit (FOM) is narrow

(Register 6, Bit 19 = 1).

Loss of Lock (LOL) Enable

When loss of lock is enabled, if digital lock detect is asserted,

and the reference signal is removed, digital lock detect goes low.

Set Register 6, Bit 18 = 1 to enable loss of lock (recommended).

Sigma-Delta (SD) Reset

When Register 6, Bit 17 = 0 on a write to Register 0, the SDM is

temporarily set to a fractional value of 0. The SD reset ensures a

consistent fractional spur pattern but also results in a glitch in

the output frequency when the N divider momentarily outputs

FRAC = 0. Remove this glitch by setting Register 6, Bit 17 = 1

(recommended setting).

CP Tristate

When Register 6, Bit 16 = 0, the phase detector operates but the

charge pump output is tristate.

Lock Detect Precision (LDP)

sensitivity of the digital lock detector. Lock detect precision

(Register 6, Bits[9:8]) in conjunction with lock detector bias

(Register 9, Bits[31:30]) adjusts the width of the digital lock

detector window. Lock is declared when the PFD reference

arrival time and divided VCO input arrival times consistently

differ by less than the LDP value. Small LDP settings may cause

a false out of lock indication when used with large bleed

currents. See the Lock Detector section for more information.

Phase Detector (PD) Polarity

If using a noninverting loop filter and a VCO with a positive

tuning slope, set PD polarity to positive.

If using an inverting loop filter and a VCO with a negative

tuning slope, set PD polarity to positive.

If using a noninverting loop filter and a VCO with a negative

tuning slope, set PD polarity to negative.

If using an inverting loop filter and a VCO with a positive

tuning slope, set PD polarity to negative.

Power Down

Set Register 6, Bit 6 = 1 to perform a software power-down. All

circuit blocks are disabled and the chip enters a low power state

drawing approximately 3 mA. Set Register 6, Bit 6 = 0 to reenable

the chip. Register values are not lost during power-down. Only

one power-down mode is available via Register 11, Bit 31. Set

regulator on during power-down.

CP Three-State

Setting Register 6, Bit 5 = 1 tristates the charge pump output.

Set Register 5, Bit 5 = 0 for normal operation.

Counter Reset

Setting Register 6, Bit 4 = 1 holds the N divider and R counter

in reset. For example, there are no signals going to the PFD.

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