ADF41513 datasheet(26/33 Pages) AD

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ADF41513

Preliminary Technical Data

Rev. PrL | Page 26 of 33

Lock Detector Count (LD COUNT)

Initial value of the lock detect counter. See operation of the lock

detector in the Lock Detector section for more information.

Lock Detect Clock Select (LD CLK SEL)

The lock detector checks for lock on every phase comparison

cycle when LD CLK SEL = 1. Otherwise, the lock detector

checks for lock on every 32nd cycle. Use LD CLK SEL = 1 to

speed up declaration of lock at the cost of reduced lock

indication stability during frequency changes.

SDM to N Divider Timing Adjustment (N Delay)

This control adjusts the timing between the SDM output and

the N divider. Set these bits to 0b01.

Prescaler Bias (PS BIAS)

Set these bits to 0b10.

CLK Divider Mode

Setting Register 7, Bits[19:18] = 0b10 enables phase resync. See

the Phase Resync section for more information.

When not using phase resync, set Register 7, Bits[19:18] = 0b00.

CLK2 Divider Value

controls the timing of the phase resync pulse. See the Phase

Resync section for more information.

CLOCK 2 REGISTER (R7)

12-BIT CLK2 DIVIDER VALUE

CN3

CN2 CN1 LD1

ND2

ND1

PB2 PB1

D12

D11

D10

CLK

DIV

MODE

CONTROL

BITS

DB17 DB16 ...

DB7 DB6

...

4,092

4,093

4,094

4,095

CLK2 DIVIDER VALUE

CLK DIV MODE

CLK DIVIDER OFF

RESERVED

PHASE RESYNC

RESERVED

CN2

LOCK DETECTOR COUNT

CN1

CN3

128

256

LOCK DETECTOR CLOCK SELECT

fPFD ÷ 32

LD1

fPFD

PS BIAS

N DELAY

PB2

PRESCALER BIAS

RESERVED

PB1

RESERVED

PROGRAM THIS VALUE

ND2

SDM TO N DELAY

RESERVED

ND1

RESERVED

PROGRAM THIS VALUE

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7 DB6

DB5 DB4

DB3 DB2

DB1 DB0

C3(1)

C4(0)

C2(1) C1(1)

Figure 28. Register 7 (R7) Map

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