CY28400OC datasheet(8/14 Pages) CYPRESS

8 / 14 page

CY28400

Document #: 38-07591 Rev. **

Page 8 of 14

Output Enable Clarification

The outputs may be disabled in two ways, via writing a ‘0’ to

SMBus register bit corresponding to output of interest or by

asserting an OE input pin low. In both methods, if SMBus

registered bit has been written low or the OE pin is low or both,

the output of interest will be three-stated. The assertion and

deassertion of this signal is asynchronous.

OE Assertion (Transition from ‘0’ to ‘1’)

All differential outputs that were three-stated will resume

normal operation in a glitch-free manner. The maximum

latency from the assertion to active outputs is between 2–6 DIF

clock periods. In addition, DIFT clocks will be driven high within

10 ns of OE assertion to a voltage greater than 200 mV.

OE Deassertion (Transition from ‘1’ to ‘0’)

The impact of de- asserting OE is each corresponding output

will transition from normal operation to three-state in a

glitch-free manner. The maximum latency from the

deassertion to three-stated outputs is between 2–6 DIF clock

periods.

SRC_DIV2# Clarification

The SRC_DIV2# feature is used to configure the DIF output

mode to be equal to the SRCT_IN input frequency or half the

input frequency in a glitch-free manner. The SRC_DIV2#

function may be implemented by writing a ‘0’ to SMBus register

bit.

SRC_DIV2# Assertion

The impact of writing a ‘0’ to the SRC_DIV/2 register bit is all

DIF outputs will transition cleanly in a glitch-free manner from

normal operation (output frequency equal to input) to half the

input frequency within 2–6 DIF clock periods.

DIFC (Stoppable)

DIFC(Free Running

DIFT(Free Running

PWRDWN#

1mS

SRC_STOP#

DIFT (Stoppable)

Figure 6. SRC_STOP# = Three-state, PWRDWN# = Driven

DIFC(Free Running

DIFT(Free Running

DIFT (Stoppable)

DIFC (Stoppable)

PWRDWN#

1mS

SRC_STOP#

Figure 7. SRC_STOP# = Three-state, PWRDWN# = Three-state

Table 6. OE Functionality

OE (Pin)

OE (SMBus Bit)

DIFT

DIFC

Normal

Three-state

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