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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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STC89LE53RC Datenblatt(PDF) 82 Page - STCmicro Technology Co,.Ltd |
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STC89LE53RC Datenblatt(HTML) 82 Page - STCmicro Technology Co,.Ltd |
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82 / 165 page  TCON register: Timer/Counter Control Register TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 (MSB) (LSB) Symbol Position Name and Significance Symbol Position Name and Significance TF1 TCON.7 Timer 1 overflow Flag. Set by hardware on Timer/Counter overflow. cleared by hardware when processor vectors to interrupt routine. IE1 TCON.3 Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected.Cleared when interrupt processed. TR1 TCON.6 Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter on/off. IT1 TCON.2 Intenupt 1 Type control bit. Set/ cleared by software to specify falling edge/low level triggered external interrupts. TF0 TCON.5 Timer 0 overflow Flag. Set by hardware on Timer/Counter overflow. cleared by hardware when processor vectors to interrupt routine. IE0 TCON.1 Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected.Cleared when interrupt processed. TR0 TCON.4 Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter on/off. IT0 TCON.0 Intenupt 0 Type control bit. Set/ cleared by software to specify falling edge/low level triggered external interrupts. SCON register LSB bit 7654321 0 name SM0/FE SM1 SM2 REN TB8 RB8 TI RI FE: Framing Error bit. The SMOD0 bit must be set to enable access to the FE bit 0: The FE bit is not cleared by valid frames but should be cleared by software. 1: This bit set by the receiver when an invalid stop bit id detected. SM0,SM1 : Serial Port Mode Bit 0/1. SM0 SM1 Description Baud rate 0 0 8-bit shift register SYSclk/12 0 1 8-bit UART variable 1 0 9-bit UART SYSclk/64 or SYSclk/32(SMOD=1) 1 1 9-bit UART variable SM2 : Enable the automatic address recognition feature in mode 2 and 3. If SM2=1, RI will not be set unless the received 9th data bit is 1, indicating an address, and the received byte is a Given or Broadcast address. In mode1, if SM2=1 then RI will not be set unless a valid stop Bit was received, and the received byte is a Given or Broadcast address. In mode 0, SM2 should be 0. REN : When set enables serial reception. TB8 : The 9th data bit which will be transmitted in mode 2 and 3. RB8 : In mode 2 and 3, the received 9th data bit will go into this bit. TI : Transmit interrupt flag. RI : Receive interrupt flag. 82 |
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