STC89LE53RC datasheet(83/165 Pages) STC

83 / 165 page

T2CON: Timer/Counter 2 Control register

LSB

bit

name

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2

CP/RL2

TF2 : Timer 2 overflow flag. TF2 is set by a Timer 2 overflow happens and must be cleared by software. TF2

will not be set when either RCLK=1 or TCLK=1.

EXF2 : Timer 2 external flag. Timer 2 external flag set when either a capture or reload is caused by a negative

transition on T2EX(P1.1) pin and EXEN2=1. When Timer 2 interrupt is enabled, EXF2=1 will cause the

CPU to vector the Timer 2 interrupt routine. EXF2 must be cleared by software.EXF2 does not cause an

interrupt in up/down mode(DCEN=1).

RCLK : Receive clock flag. When set, cause the serial port to use Timer 2 overflow pulses for its receive clock in

modes 1 and 3. When cleared, cause Timer 1 overflow to be used for the receive clock.

TCLK : Transmit clock flag.When set, cause the serial port to use Timer 2 overflow pulses for its transmit clock

in modes 1 and 3. When cleared, cause Timer 1 overflows to be used for the transmit clock.

EXEN2 : Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative

transition on T2EX(P1.1) pin if Timer 2 is not being used to clock the serial port. When cleared, cause

Timer 2 to ignore events at T2EX(P1.1) pin.

TR2 : Timer 2 Run control bit.When set, start the Timer 2. When cleared, stop the Timer 2.

C/T2: Timer or counter selector.

0: Select Timer 2 as internal timer function.

1: Select Timer 2 as external event counter (falling edge triggered).

CP/RL2: Capture/Reload flag.

0 : Auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX pin when EXEN2=1.

1 : Captures will occur on negative transitions at T2EX pin if EXEN2=1.

XICON: Auxiliary Interrupt Control register

LSB

bit

B7B6B5B4B3B2B1B0

name

PX3

EX3

IE3

IT3

PX2

EX2

IE2

IT2

PX3 : If set, Set priority for external interrupt 3 higher

EX3 : If set, Enables external interrupt 3.

IE3 : External Interrupt 3 Edge flag. Sets by hardware when external interrupt edge detected.Cleared by hardware

when interrupt is starting to be serviced.

IT3 : External Interrupt 3 type control bit. Set/Cleared by software to specified falling edge/low level triggered

interrupt.

PX2 : If set, Set priority for external interrupt 3 higher

EX2 : If set, enables external interrupt 2.

IE2 : External Interrupt 2 Edge flag. Sets by hardware when external interrupt edge detected. Cleared when

interrupt is starting to be serviced.

IT2 : Interrupt 2 types control bit. Set/Cleared by software to specify falling edge/low level triggered interrupt.

IP (or XICON) and IPH are combined to form 4-level priority interrupt as the following table.

{IPH.x, IP.x/XICON.x} Priority Level

1,1

0(highest)

1,0

0,1

0,0

STC89LE53RC Datenblatt(PDF) 83 Page - STCmicro Technology Co,.Ltd

STC89LE53RC Datenblatt(HTML) 83 Page - STCmicro Technology Co,.Ltd

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL