ADHV4702-1BCPZ-R7 datasheet(15/21 Pages) AD

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Data Sheet

ADHV4702-1

Rev. A | Page 15 of 21

THEORY OF OPERATION

The ADHV4702-1 is a high voltage (220 V) precision amplifier

designed using the next generation of proprietary bipolar/

complementary metal-oxide semiconductor (CMOS)/laterally

diffused metal-oxide semiconductor (BCDMOS) process from

Analog Devices. Figure 3 shows the functional block diagram.

The input stage architecture offers the advantages of high input

impedance with low input bias current, low input offset voltage,

low drift, and low noise for precision demanding applications,

such as automated test equipment (ATE).

INTERNAL ELECTROSTATIC DISCHARGE (ESD)

PROTECTION

As shown in Figure 43, the ADHV4702-1 has an internal ESD

configuration to prevent damage due to overvoltage. The ESD

protection circuitry involves current steering diodes connected

from the input and output pins to the power supply rails. The

ADHV4702-1 also includes internal input clamping diodes across

the inverting and noninverting inputs to prevent large differential

input voltages from damaging the input stage transistors. This

input clamping circuit greatly reduces the input impedance for

differential input voltages greater than the forward-biased

voltage (VF) of four diodes.

The ESD protection circuitry remains inactive under normal

operation. To avoid forward biasing the ESD diodes, do not

overdrive the pin voltages above the absolute maximum ratings,

and ensure that the input differential voltage does not exceed

4 VF. Additional external input clamping diodes may be

required to protect the slew boost circuit. See the Slew Boost

Circuit and Protection section.

225V ESD

DGND

~5V

DGND

~5V

125Ω

DGND

~5V

DGND

~5V

DGND

VEE VCC

125Ω

DGND

COMP

IN–

RESERVED

IN+

RESERVED

OUT

TMP

VEE

VCC

RADJ

Figure 43. Simplified ESD Configuration

SLEW BOOST CIRCUIT AND PROTECTION

The ADHV4702-1 uses a supplementary slew boosting circuit

to achieve its typical slew rate of 74 V/µs across a 200 V p-p

output range at unity gain. This slew boosting circuit works by

sensing the differential input voltage of the amplifier and

converting this voltage into a dynamic current to help drive

capacitances within the signal path of the amplifier. With

greater input voltage across the inputs, more dynamic current is

produced, which enables the amplifier to slew faster. The

current produced by the slew boosting circuit transmits to all

stages of the amplifier during slewing.

Internally, the ADHV4702-1 contains differential input voltage

clamps that limit transient differential signals to 4 VF, placing an

upper limit on the slew boost. Large differential input voltages

(which can be occur with signal frequencies approaching the

full power bandwidth) trigger the slew boosting circuit,

resulting in an increased dynamic supply current. The

relationship between slew rate and full power bandwidth (fM) is

given in the following equation:

SR = VO × 2πfM

where VO is the peak output voltage.

When operating continuously at or near full power bandwidth,

the increased supply current may cause an increase in TJ

beyond the safe operating temperature, resulting in device

damage. The dynamic safe operating area (SOA) for the EVAL-

ADHV4702-1CPZ evaluation board is shown in Figure 59 in

the Safe Operating Area section. The dynamic SOA shows the

connection between the output swing and the maximum

input/output frequency for pulse response. To expand the SOA

curve, use additional thermal management or limit the

differential voltage across the inputs to 2 VF with external

diodes, which limits the current produced by the slew boosting

circuit and reduces the internal power dissipation. Clamping

the differential input voltage of the ADHV4702-1 in this way

protects the amplifier in dynamic operation but limits slew rate

and large signal bandwidth. Figure 44 shows a simplified

schematic with external input clamping diodes, and Figure 45 to

Figure 48 show the large signal pulse response at various

temperatures and gains while the ADHV4702-1 inputs are

clamped by two ON Semiconductor SBAV199LT1G diode pairs

at 2 VF.

ADHV4702-1

5kΩ

VIN

100kΩ

10kΩ

VOUT

EXTERNAL

INPUT

CLAMPING

DIODES

Figure 44. External Input Clamping Diodes Schematic

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