CBM708 datasheet(6/18 Pages) COREBAI

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CBM705/CBM706/CBM707/CBM708

OPERATION INSTRUCTION

Pin Function Descriptions

Mnemonic

Pin Number

Description

CBM705

CBM706

CBM707

CBM708

Manual Reset Input. When this pin is taken below 0.8V, a reset is

generated. MR can be driven from TTL, CMOS logic, or from a manual

reset switch as it is internally debounced. An internal 250μA pull-up

current holds the input high when floating.

VCC

5V Power Supply Input. Place a 0.1μF decoupling capacitor between the

VCC and GND pins.

GND

0V Ground Reference for All Signals.

PFI

Power Fail Input. PFI is the noninverting input to the power fail

comparator. When PFI is less than 1.25V, PFO goes low. If unused, PFI

must be connected to GND.

PFO

Power Fail Output. PFO is the output from the power fail comparator. It

goes low when PFI is less than 1.25V.

WDI

Not

applicable

Not

applicable

Watchdog Input. WDI is a three-level input. If WDI remains either high or

low for longer than the watchdog timeout period, the watchdog output

(WDO) goes low. The timer resets with each transition at the WDI input.

Either a high to low or a low to high transition clears the counter. The

internal timer is also cleared whenever reset is asserted. The watchdog

timer is disabled when WDI is left floating or connected to a three-state

buffer.

Not

applicable

No Connect.

RESET

Logic Output. RESET goes low for 200ms when triggered. It can be

triggered either by VCC being below the reset threshold or by a low signal

on the manual reset input ( MR ). RESET remains low whenever VCC is

below the reset threshold (4.65V in CBM705/CBM707, 4.40 V in

CBM706/CBM708). It remains low for 200ms after VCC goes above the

reset threshold or MR goes from low to high. A watchdog timeout does

not trigger RESET unless WDO is connected to MR.

WDO

Not

applicable

Not

applicable

Watchdog Output. WDO remains low until the watchdog timer is cleared.

WDO also goes low during low line conditions. Whenever VCC is below the

reset threshold, WDO goes low if the internal WDO remains low. As

soon as VCC goes above the reset threshold, WDO goes high.

RESET

Not

applicable

Logic Output. RESET is an active high output suitable for systems that use

active high reset logic. It is the inverse of RESET.

CBM708 Datenblatt(PDF) 6 Page - COREBAI Microelectronics (Beijing) Co., Ltd.

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