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CBM705/CBM706/CBM707/CBM708

OPERATION INSTRUCTION

WATCHDOG TIMER (CBM705/CBM706)

The watchdog timer circuit can monitor the activity of the micro-processor to check that it is

not stalled in an indefinite loop. An output line on the processor toggles the watchdog input

(WDI) line. If this line is not toggled within the timeout period (1.60 sec), then the watchdog

output (WDO) goes low. The WDO can be connected to a nonmaskable interrupt (NMI) on the

processor; therefore, if the watchdog timer times out, an interrupt is gen-erated. The interrupt

service routine then rectifies the problem.

If a RESET signal is required when a timeout occurs, the WDO must connect to the manual

reset input (MR).

The watchdog timer is cleared by either a high to low or a low to high transition on WDI. It is

also cleared by RESET going low; therefore, the watchdog timeout period begins after RESET

goes high.

timer has timed out. Normally, this generates an interrupt, but it is overridden by RESET going

low.

The watchdog monitor can be deactivated by floating the WDI. The WDO can then be used

Figure 14. Watchdog Timing