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STR720RBQ6 Datenblatt(PDF) 60 Page - STMicroelectronics |
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STR720RBQ6 Datenblatt(HTML) 60 Page - STMicroelectronics |
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60 / 401 page ![]() STR720 - ENHANCED INTERRUPT CONTROLLER (EIC) 60/401 • IVR(31:0) contains an instruction In the first case (address), IVR(31:16) will have to be loaded with the higher part of the address pointing to the memory location where the interrupt service routines begin; the single SIRn(31:16) will have to contain the lower 16 bits (offset) of the memory address related to the channel specific ISR. If required and supported by the system/processor configuration, it can also be convenient to initialize IVR(31:16) and SIRn(31:16) to provide an instruction opcode (typically a jump) on IVR register read. In this situation, IVR(31:16) has to contain the higher part of the instruction to be passed, while SIRn(31:16) will be loaded with the channel depending parameters (usually jump offset). 1 |
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