STR720RBQ6 datasheet(19/401 Pages) STMICROELECTRONICS

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STR720 - PIN DATA

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4.8 Main Clock input pins

4.9 Port 6 pins

Port 6 is a configurable 8/16/32-bit interface port used by the Synchronous DRAM memory

interface. DRAMC is under STR720 control through configuration registers. Port lines are

permanently assigned to the relevant pins and they are listed in the following table.

Table 9. Main Clock Input Pins

Symbol

Pin)

I/O

Function

CLK

I-P

This pin is used as main system clock source.

I-P

Reserved, must be tied to GND.

I-P

Reserved, must be tied to GND.

I-P

Reserved, must be tied to GND.

VREF

CLK input reference voltage

Table 10. Port 6 Pins

Symbol

I/O

Function

P6.0

108

I/O

SDRAM Data line 0 (Mid[0]).

P6.1

107

I/O

SDRAM Data line 1 (Mid[1]).

P6.2

106

I/O

SDRAM Data line 2 (Mid[2]).

P6.3

105

I/O

SDRAM Data line 3 (Mid[3]).

P6.4

102

I/O

SDRAM Data line 4 (Mid[4]).

P6.5

101

I/O

SDRAM Data line 5 (Mid[5]).

P6.6

100

I/O

SDRAM Data line 6 (Mid[6]).

P6.7

I/O

SDRAM Data line 7 (Mid[7]).

P6.8

118

I/O

SDRAM Data line 8 (Mid[8]).

P6.9

117

I/O

SDRAM Data line 9 (Mid[9]).

P6.10

116

I/O

SDRAM Data line 10 (Mid[10]).

P6.11

115

I/O

SDRAM Data line 11 (Mid[11]).

P6.12

112

I/O

SDRAM Data line 12 (Mid[12]).

P6.13

111

I/O

SDRAM Data line 13 (Mid[13]).

P6.14

110

I/O

SDRAM Data line 14 (Mid[14]).

P6.15

109

I/O

SDRAM Data line 15 (Mid[15]).

P6.16

I/O

SDRAM Data line 16 (Mid[16]).

P6.17

I/O

SDRAM Data line 17 (Mid[17]).

P6.18

I/O

SDRAM Data line 18 (Mid[18]).

P6.19

I/O

SDRAM Data line 19 (Mid[19]).

P6.20

I/O

SDRAM Data line 20 (Mid[20]).

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