5CSXFC6D6F31C8N datasheet(70/93 Pages) INTEL

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Configuration Scheme

Encryption

Compression

DCLK-to-DATA[] Ratio (r)

Off

FPP Configuration Timing when DCLK-to-DATA[] = 1

When you enable decompression or the design security feature, the DCLK-to-DATA[] ratio varies for FPP ×8 and FPP ×16. For

the respective DCLK-to-DATA[] ratio, refer to the DCLK-to-DATA[] Ratio for Cyclone V Devices table.

Table 58.

FPP Timing Parameters When DCLK-to-DATA[] Ratio is 1 for Cyclone V Devices

Symbol

Parameter

Minimum

Maximum

Unit

tCF2CD

nCONFIG

low to CONF_DONE low

—

600

tCF2ST0

nCONFIG

low to nSTATUS low

—

600

tCFG

nCONFIG

low pulse width

—

µs

tSTATUS

nSTATUS

low pulse width

268

1506(77)

µs

tCF2ST1

nCONFIG

high to nSTATUS high

—

1506(78)

µs

tCF2CK(79)

nCONFIG

high to first rising edge on DCLK

1506

—

µs

tST2CK(79)

nSTATUS

high to first rising edge of DCLK

—

µs

tDSU

DATA[]

setup time before rising edge on DCLK

5.5

—

tDH

DATA[]

hold time after rising edge on DCLK

—

tCH

DCLK

high time

0.45 × 1/fMAX

—

continued...

(77) You can obtain this value if you do not delay configuration by extending the nCONFIG or the nSTATUS low pulse width.

(78) You can obtain this value if you do not delay configuration by externally holding the nSTATUS low.

(79) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification.

Cyclone V Device Datasheet

CV-51002 | 2019.01.25

Cyclone V Device Datasheet

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