5CSXFC6D6F31C8N datasheet(49/93 Pages) INTEL

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DLL Frequency Range Specifications

Table 35.

DLL Frequency Range Specifications for Cyclone V Devices

Parameter

–C6

–C7, –I7

–C8

Unit

DLL operating frequency range

167 – 400

167 – 333

MHz

DQS Logic Block Specifications

Table 36.

DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Cyclone V Devices

This error specification is the absolute maximum and minimum error.

Number of DQS Delay Buffer

–C6

–C7, –I7

–C8

Unit

Memory Output Clock Jitter Specifications

Table 37.

Memory Output Clock Jitter Specifications for Cyclone V Devices

The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.

The memory output clock jitter is applicable when an input jitter of 30 ps (p-p) is applied with bit error rate (BER) 10–12, equivalent to 14 sigma.

Intel recommends using the UniPHY intellectual property (IP) with PHYCLK connections for better jitter performance.

Parameter

Clock Network

Symbol

–C6

–C7, –I7

–C8

Unit

Min

Max

Min

Max

Min

Max

Clock period jitter

PHYCLK

tJIT(per)

–60

–70

Cycle-to-cycle period jitter

PHYCLK

tJIT(cc)

—

100

—

100

Cyclone V Device Datasheet

CV-51002 | 2019.01.25

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Cyclone V Device Datasheet

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