STM8S datasheet(75/467 Pages) STMICROELECTRONICS

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RM0016

Reset (RST)

104

An internal temporization maintains a pulse of duration tOP(NRST) whatever the internal reset

source. An additional internal weak pull-up ensures a high level on the reset pin when the

reset is not forced.

8.3

Internal reset sources

Each internal reset source is linked to a specific flag bit in the Reset status register

(RST_SR) except POR/BOR which have no flag. These flags are set respectively at reset

depending on the given reset source. So they are used to identify the last reset source.

They are cleared by software writing the logic value “1”.

8.3.1

Power-on reset (POR) and brown-out reset (BOR)

During power-on, the POR keeps the device under reset until the supply voltages (VDD and

VDDIO) reach the voltage level at which the BOR starts to function. At this point, the BOR

reset replaces the POR and the POR is automatically switched off. The BOR reset is

maintained till the supply voltage reaches the operating voltage range.

See Electrical parameters section of the datasheet for more details.

The BOR also generates a reset when the supply voltage drops below the VIT- threshold.

When this occurs, the POR is re-armed for the next power-on phase.

An hysteresis is implemented to ensure clean detection of voltage rise and fall.

The BOR always remains active even when the MCU is put into Low Power mode.

Figure 19. VDD/VDDIO voltage detection: POR/BOR threshold

8.3.2

Watchdog reset

Refer to Section 15: Window watchdog (WWDG) and Section 14: Independent watchdog

(IWDG) for details.

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