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STM8S Datenblatt(PDF) 25 Page - STMicroelectronics

Teilenummer STM8S
Bauteilbeschribung  STM8S Series and STM8AF Series 8-bit microcontrollers
PDF  467 Pages
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STM8S Datenblatt(HTML) 25 Page - STMicroelectronics

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RM0016
Central processing unit (CPU)
28
Figure 2. Stacking order
Condition code register (CC)
The condition code register is an 8-bit register which indicates the result of the instruction
just executed as well as the state of the processor. The 6th bit (MSB) of this register is
reserved. These bits can be individually tested by a program and specified action taken as a
result of their state. The following paragraphs describe each bit:
V: Overflow
When set, V indicates that an overflow occurred during the last signed arithmetic operation,
on the MSB result bit. See the INC, INCW, DEC, DECW, NEG, NEGW, ADD, ADDW, ADC,
SUB, SUBW, SBC, CP, and CPW instructions.
I1: Interrupt mask level 1
The I1 flag works in conjunction with the I0 flag to define the current interruptability level as
shown in Table 1. These flags can be set and cleared by software through the RIM, SIM,
HALT, WFI, IRET, TRAP, and POP instructions and are automatically set by hardware when
entering an interrupt service routine.



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