AT21CS01 datasheet(33/47 Pages) MICROCHIP

33 / 47 page

This sequence begins by the master sending a Start condition, followed by a device address byte with the

opcode of 7h in the four Most Significant bits, along with the appropriate slave address combination and

the Read/Write bit set to a logic ‘0’. The AT21CS01/11 will respond with an ACK.

Following this device address byte is an 8-bit ROM Zone register address byte. The four Most Significant

bits are not used and are therefore "don’t care" bits. The address sent to the device must match one of

the ROM Zone register addresses specified in Table 8-3. After the ROM Zone register address has been

sent, the AT21CS01/11 will return an ACK (logic ‘0’).

Then an additional Start condition is sent to the device with the same device address byte as before, but

now with the Read/Write bit set to a logic ‘1’, to which the device will return an ACK. After the

AT21CS01/11 has sent the ACK, the device will output either 00h or FFh data byte. A 00h data byte

indicates that the ROM Zone register is zero, meaning the zone has not been set as ROM. If the device

outputs FFh data, then the memory zone has been set to ROM and cannot be altered.

Table 8-3. Read ROM Zone Register – Output Data

Output Data

ROM Zone Register Value

00h

ROM Zone register value is zero (zone is not set as ROM).

FFh

ROM Zone register value is one (zone is permanently set as ROM).

Figure 8-1. Reading the State of a ROM Zone Register

SI/O

MSB

ACK

by Slave

1 A2 A1 A0 0

Device Address

Dummy Write

MSB

0 A3 A2 A1 A0

ROM Zone Register Address

MSB

Data Out Byte (00h or FFh)

ACK

by Slave

NACK

by Master

Stop Condition

by Master

Start Condition

by Master

MSB

ACK

by Slave

1 A2 A1 A0 1

Device Address

Restart

by Master

8.2.2

Writing to a ROM Zone Register

A ROM Zone register can only be written to a logic ‘1’ which will set the corresponding memory zone to a

ROM state. Once a ROM Zone register has been written, it can never be altered again.

To write to a ROM Zone register, the master must send a Start condition, followed by the device address

byte with the opcode of 0111b (7h) specified, along with the appropriate slave address combination and

the Read/Write bit set to a logic ‘0’. The device will return an ACK. After the device address byte has

been sent, the AT21CS01/11 will return an ACK.

Following the device address byte is an 8-bit ROM Zone register address byte. The address sent to the

device must match one of the ROM Zone register addresses specified in Table 8-2. After the ROM Zone

After the AT21CS01/11 has sent the ACK, the master must send an FFh data byte in order to set the

appropriate ROM Zone register to the logic ‘1’ state. The device will then return an ACK and, after a Stop

condition is executed, the device will enter a self-time internal write cycle, lasting tWR. If a Stop condition

is sent at any other point in the sequence, the write operation to the ROM Zone register is aborted. The

device will not respond till any commands until the tWR time has completed. This sequence is depicted in

Figure 8-2.

AT21CS01/AT21CS11

Datasheet

DS20005857A-page 33

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