AT21CS01 datasheet(14/47 Pages) MICROCHIP

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3.1.3

Data Input and Output Bit Frames

Communication with the AT21CS01/11 is conducted in time intervals referred to as a bit frame and lasts

tBIT in duration. Each bit frame contains a single binary data value. Input bit frames are used to transmit

data from the master to the AT21CS01/11 and can either be a logic ‘0’ or a logic ‘1’. An output bit frame

carries data from the AT21CS01/11 to the master. In all input and output cases, the master initiates the bit

frame by driving the SI/O line low. Once the AT21CS01/11 detects the SI/O being driven below the VIL

level, its internal timing circuits begin to run.

The duration of each bit frame is allowed to vary from bit to bit as long as the variation does not cause the

tBIT length to exceed the specified minimum and maximum values (see AT21CS01/11 AC

Characteristics). The tBIT requirements will vary depending on whether the device is set for Low-Speed or

High-Speed mode. For more information about setting the speed of the device, refer to Setting the Device

Speed.

3.1.3.1

Data Input Bit Frames

A data input bit frame can be used by the master to transmit either a logic ‘0’ or logic ‘1’ data bit to the

AT21CS01/11. The input bit frame is initiated when the master drives the SI/O line low. The length of time

that the SI/O line is held low will dictate whether the master is transmitting a logic ‘0’ or a logic ‘1’ for that

bit frame. For a logic ‘0’ input, the length of time that the SI/O line must be held low is defined as tLOW0.

Similarly, for a logic ‘1’ input, the length of time that the SI/O line must be held low is defined as tLOW1.

The AT21CS01/11 will sample the state of the SI/O line after the maximum tLOW1 but prior to the minimum

tLOW0 after SI/O was driven below the VIL threshold to determine if the data input is a logic ‘0’ or a

logic ‘1’. If the master is still driving the line low at the sample time, the AT21CS01/11 will decode that bit

frame as a logic ‘0’ as SI/O will be at a voltage less than VIL. If the master has already released the SI/O

line, the AT21CS01/11 will see a voltage level greater than or equal to VIH because of the external pull-up

resistor, and that bit frame will be decoded as a logic ‘1’. The timing requirements for these parameters

can be found in AT21CS01/11 AC Characteristics.

A logic ‘0’ condition has multiple uses in the I2C emulation sequences. It is used to signify a ‘0’ data bit,

and it also is used for an Acknowledge (ACK) response. Additionally, a logic ‘1’ condition is also is used

for a No Acknowledge (NACK) response in addition to the nominal ‘1‘ data bit.

Figure 3-2 and Figure 3-3 depict the logic ‘0’ and logic ‘1’ input bit frames.

Figure 3-2. Logic 0 Input Condition Waveform

SI/O

tLOW0

VIL

VIH

tBIT

MASTER

PULL-UP RESISTOR

tRCV

AT21CS01/AT21CS11

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