ADAV801ASTZ datasheet(30/56 Pages) AD

30 / 56 page

ADAV801

Rev. 0 | Page 30 of 56

ADAV801 has a d

cated contro

ort to allow access to

AV801. Each of the internal

ght bits w

s reserved

these bits shoul

ACE

ontrol of the ADAV8

l port is

ycle of data transfer c

s. Figure 53 shows the

rmat of an SPI write

The transfer of

ata is initiated on the

ATCH. The data

resented on the first s

ents the register

rite bit.

f data are loaded to th

provided. If this bit is

h, a read operation is indicated. The contents of the register

ess are clocked ou

n on the following eight

CLKs. For a read ope

ts after the read/write

BLOCK EADS AN

The ADAV801 provides the user with the ability to write to or

read from a block of registers in one continuous operation. In

SPI mode, the CLATCH line should be held low for longer than

the 16 CCLK periods to use the block read/write mode. For a

write operation, once the LSB has been clocked into the

ADAV801 on the 16th CCLK, the register address as specified

by the first seven bits of the write operation is incremented and

the next eight bits are clocked into the next register address.

The read operation is similar. Once the LSB of a read register

operation has been clocked out, the register address is

incremented and the data from the next register is clocked out

on the following eight CCLKs. Figure 55 and Figure 56 show the

timing diagrams for the block write and read operations.

INTERFACE CONTROL

The

edi

l p

the internal registers of the AD

registers is ei

ide. Where bits are described a

(RES),

d be programmed as zero.

SPI INTERF

01 is via an SPI-compatible serial port

The SPI contro

a 4-wire serial control port with one

onsisting of 16 bit

/read of the ADAV801.

falling edge of CL

even CCLKs repres

address read/w

If this bit is low, the following eight bits

e register address

hig

addr

t on the COUT pi

ration, the data bi

bits are ignored.

D WRITES

CLATCH

CCLK

CIN

D14

COUT

D15

SPI Serial Port Timing Diagram

Figure 53.

987

6543

210

R/W

ADDRESS [6:0]

DATA [7:0]

re 54. SPI C

orm

Figu

ontrol Word F

R/W = 0

8 BITS

CLATCH

CIN

8 BITS

Figure 55. SPI Block Write Operation

R/W = 1

8 BITS

CLATCH

CIN

DON’T CARE

Figure 56. SPI Block Read Operation

OUT

ADAV801ASTZ Datenblatt(PDF) 30 Page - Analog Devices

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