ADAV801ASTZ datasheet(49/56 Pages) AD

49 / 56 page

ADAV801

Rev. 0 | Page 49 of 56

LK1

LK0

DIV

Table 73. PLL Control Register 1

DIRIN_C

MCLKO

PLLDIV

PLL2PD

PLL1PD

XTLPD

SYSCLK3

ADDRESS = 1110100 (0x74)

DIRIN_CLK1-0

nt to SYSCLK3.

Recovered SPDIF clock se

00 = SYSCLK3 comes from PLL block.

the recovered SPDIF clock from DIRIN.

CLKODIV

generate MCLKO.

y 2 to generate the PLL master clock.

LL2.

own.

n XTAL oscillator.

down.

for SYSCLK3.

01 = Reserved

10 = Reserved.

11 = SYSCLK3 is

Divide input MCLK by 2 to

0 = Disabled.

1 = Enabled

PLLDIV

Divide XIN b

0 = Disabled.

1 = Enabled

PLL2PD

Power-down P

0 = Normal.

1 = Power-down.

PLL1PD

Power-down PLL1.

0 = Normal.

1 = Power-d

XTLPD

Power-dow

0 = Normal.

1 = Power-

SYSCLK3

Clock output

0 = 512 × fS.

1 = 256 × fS.

Table 74. PLL Control Register 2

SEL2

DOUB2

FS1

FS0

SEL1

DOUB1

FS2_1

FS2_0

ADDRESS = 1110101 (0x75)

FS2_1–0

Sampl rate se

t for PLL2.

lec

00 = 48 kHz.

io select for PLL2.

UB2

lected sample rate on PLL2.

select for PLL1.

rved.

11 = 44.1 kHz.

SEL1

Oversample ratio select for PLL1.

0 = 256 × fS.

1 = 384 × fS.

DOUB1

Double-selected sample rate on PLL1.

0 = Disabled.

1 = Enabled.

01 = Reserved.

10 = 32 kH

11 = 44.1 kHz

SEL2

Oversample rat

0 = 256 × fS.

1 = 384 × fS.

Double-se

0 = Disabled.

1 = Enable

FS1–0

Sample rate

00 = 48 kHz.

01 = Rese

10 = 32 kHz

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