ADAV801ASTZ datasheet(25/56 Pages) AD

25 / 56 page

ADAV801

Rev. 0 | Page 25 of 56

Data Bits

Table 10. Professional Audio Standard

Address

Sample

Frequency

Lock

Emphasis

Non-

Audio

Pro/

Con

= 1

N + 1

User Bit Management

Channel Mode

N + 2

Alignm

Level

Use of Auxiliary Mode

ent

Source Word Length

Sample Bits

N + 3

Channel Identification

N + 4

Scal-

ing

Reference

Signal

Sample Frequency (fS)

Reserved

Digital Audio

N + 5

Reserved

N + 6

Alphanumeric Channel Origin Data—First Character

N + 7

Alphanumeric Channel Origin Data

N + 8

Alphanumeric Channel Origin Data

N + 9

el Origin Data—Last Character

Alphanumeric Chann

N + 1

ion Data—First Character

A hanumeric Channel Destinat

N + 11

Alphanumeric Channel Destination Data

N + 12

Alphanumeric Channel Destination Data

N + 1

phanumeric Channel Destination Data—Last Character

N + 14

Local Sample Address Code—LSW

N + 15

Local Sample Address Code

N + 16

Local Sample Address Code

N + 17

Local Sample Address Code—MSW

N + 18

Time of Day Code—LSW

N + 19

Time of Day Code

N + 20

Time of Day Code

N + 21

Time of Day Code—MSW

N + 22

Reliability Flags

Reserved

N + 23

Cyclic Redundancy Check Character (CRCC)

N = 0x20 for receiver channel status buffer.

are

organized into 24 bytes and have the interpretations shown in

the need for user intervention.

Receiver Section

The ADAV801 uses a double-buffering scheme to handle read-

ing channel status and user bit information. The channel status

bits are available as a memory buffer, taking up 24 consecutive

memory addressing scheme, where the receiver user- bit

indirect-address register is programmed with an offset to the

iver user bit data register can be read

read

N = 0x38 for transmitter channel status buffer.

The standards allow the channel status bits in each subframe to

be independent, but ordinarily the channel status bit in the two

subframes of each frame are the same. The channel status bits

are defined differently for the consumer audio standards and

the professional audio standards. The 192 channel status bits

Table 9 and Table 10.

The SPDIF transmitter and receiver have a comprehensive

functions of the SPDIF block, such as detecting nonaudio an

validity bits, Q subcodes, preambles, and so on. The channel

status bits as defined by the IEC60958 and AES3 specifications

are stored in register buffers for ease of use. An autobuffering

function allows channel status bits and user bits read by the

receiver to be copied directly to the transmitter block, removing

user bit buffer, and the rece

to determine the user bits at that location. Reading the receiv

user bit data register automatically updates the indirect address

user bit indirect-address register is programmed to zero (the

start of the buffer), and the receiver user bit data register is

repeatedly until all the buffer’s data has been read. Figure 46 an

Figure 47 show how receiving the channel status bits and user

bits is implemented.

SECONDBUFFER

RECEIVE

CHANNEL

STATUS A

(24 × 8 BITS)

DIRIN

CS BUFFER

(0x20–0x37)

CHANNEL

STATUS B

(24 × 8 BITS)

RxCSSWITCH

SPDIF

RECEIVE

BUFFER

FIRST BUFFER

Figure 46. Channel Status Buffer

BUFFER

SPDIFIN

0...7

8...15

16...23

FIRST

0...7

8...15

16...23

USER-BIT

BUFFER

ADDRESS = 0x50

ADDRESS = 0x51

RECEIVER USER BIT

INDIRECT ADDRESS

RECEIVER USER BIT

DATA REGISTER

Figure 47. Receiver User Bit Buffer

The SPDIF receive buffer is updated continuously by the

incoming SPDIF stream. Once all the channel status bits f

block (192 for Channel A and 192 for Channel B) are recei

or the

ved,

This

d the

bi n the channel status switch buffer register

eth

equi

to be

fer is

bytes

g and

Because the chan

change, a software

T, is provided to

tify th

ost co

tatus

bits is available or

status

formation have changed from a previous block. The function

of the RxCSBINT is controlled by the RxBCONF3 bit in the

receiver buffer configuration register.

The size of the user bit buffer can be set by programming the

RxBCONF0 bit in the receiver buffer configuration register, as

shown in Table 11.

the bits are copied into the receiver channel status buffer.

buffer stores all 384 bits of channel status information, an

RxCSSWITCH

t i

determ es wh

er the Channel A or the Channel B status bits

are r

red

read. The receive channel status bit buf

lon

spans the address range from 0x20 to 0x37.

nel status bits of an SPDIF stream rarely

interrupt/flag bit, RxCSBIN

e h

ntrol that either a new block of channel s

that the first five bytes of channel

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