Data Sheet

ADRF5025

Rev. B | Page 9 of 13

THEORY OF OPERATION

The ADRF5025 requires a positive supply voltage applied to the

VDD pin and a negative supply voltage applied to the VSS pin.

Bypassing capacitors are recommended on the supply lines to

filter high frequency noise.

All of the RF ports (RFC, RF1, and RF2) are dc-coupled to 0 V,

and no dc blocking is required at the RF ports when the RF line

potential is equal to 0 V.

The RF ports are internally matched to 50 Ω. Therefore,

external matching networks are not required. However,

impedance matching on transmission lines can be used to

improve insertion loss and return loss performance at high

frequencies.

The ADRF5025 integrates a driver to perform logic functions

internally and provides the user with the advantage of a

simplified CMOS/LVTTL-compatible control interface. This

driver features a single digital control input pin, CTRL. The

logic level applied to the CTRL pin determines which RF port is

in the insertion loss state and in the isolation state (see Table 5).

The unselected RF port of the ADRF5025 is reflective. The

isolation path provides high isolation between the unselected

port and the insertion loss path.

The ideal power-up sequence is as follows:

1. Connect GND.

2. Power up VDD and VSS. Power up VSS after VDD to

avoid current transients on VDD during ramp-up.

3. Apply the digital control inputs. The relative order of the

control inputs is not important. However, powering the

digital control inputs before the VDD supply may

inadvertently forward bias and damage the internal ESD

protection structures. To avoid this damage, use a series

1 kΩ resistor to limit the current flowing in to the control

pin. Use pull-up or pull-down resistors if the controller is

in a high impedance state after VDD is powered up and

the control pins are not driven to a valid logic state.

4. Apply an RF input signal.

The ideal power-down sequence is the reverse order of the

power-up sequence.

Table 5. Control Voltage Truth Table

RF Path

RF1 to RFC

RF2 to RFC

Low

Isolation (off)

Insertion loss (on)

High

Insertion loss (on)

Isolation (off)