MCP39F511N datasheet(31/61 Pages) MICROCHIP

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DS20005473B-page 31

MCP39F511N

6.4

System Version Register

The System Version register is hard-coded by

Microchip Technology Incorporated and contains

calculation-engine date-code information. The System

Version register is a date code in the YMDD format, with

year and month in hex, day in decimal (e.g. 0xFB20 =

2015, Nov. 20th).

6.5

System Configuration Register

The System Configuration register contains bits for the

following control:

• PGA setting

• ADC Reset State

• ADC Shutdown State

• Voltage Reference Trim

• Single Wire Auto-Transmission

These options are described in the following sections.

6.5.1

PROGRAMMABLE GAIN

AMPLIFIERS (PGA)

The two Programmable Gain Amplifiers (PGAs) reside

at the front-end of each 24-bit Delta-Sigma ADC. They

have two functions:

• translate the common mode of the input from

AGND to an internal level between AGND and AVDD

• amplify the input differential signal

The translation of the common mode does not change

the differential signal, but enters the common mode so

that the input signal can be properly amplified.

The PGA block can be used to amplify very low signals,

but the differential input range of the Delta-Sigma

modulator must not be exceeded. The PGA is

controlled by the PGA_CHn<2:0> bits in Register 6-2:

the

System

Configuration

Table 6-2

represents the gain settings for the PGAs.

bit 5

SIGN_PR_CH1: Sign of Reactive Power Channel 1 (inductive/capacitive state of the reactive power)

= Reactive Power is inductive and is in quadrants 1,2

= Reactive Power is capacitive and is in quadrants 3,4

bit 4

SIGN_PA_CH1: Sign of Active Power Channel 1 (import/export sign of active power)

= Active Power is positive (import) and is in quadrants 1,4

= Active Power is negative (export) and is in quadrants 2,3

bit 3

OVERPOW1: Over Power, channel 1. An over power event has occurred on channel 1.

= Over Power threshold has been broken

= Over Power threshold has not been broken

bit 2

OVERCURR1: Over Current, channel 1. An over current event has occurred on channel 1.

= Over current threshold has been broken

= Over current threshold has not been broken

bit 1

VSURGE: Voltage Surge. State of Voltage Surge Detection algorithm. This bit is latched and must be

cleared

= Surge threshold has been broken

= Surge threshold has not been broken

bit 0

VSAG: Voltage Sag.State of Voltage Sag Detection algorithm. This bit is latched and must be cleared

= Sag threshold has been broken

= Sag threshold has not been broken

SYSTEM STATUS REGISTER (CONTINUED)

TABLE 6-2:

PGA CONFIGURATION

SETTING (Note 1)

Gain

PGA_CHn<2:0>

Gain

(V/V)

Gain

(dB)

VIN Range

(V)

±0.6

±0.3

412

±0.15

818

±0.075

±0.0375

±0.01875

Note 1: This table is defined with VREF = 1.2V.

The two undefined settings, 110 and 111

are G = 1.

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