Table 8-2. Device Address Byte Requirements for Accessing the Write Protection Register

Memory Region

Device Type Identifier

Hardware Client Address Bits

R/W Select

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Write Protection Register

1

0

1

1

A2

A1

A0

R/W

When accessing the Write Protection register, it is required that the A7 and A6 bits of the word address be set to

‘11b’ respectively. The remaining bits of the word address byte are ‘don’t care’ bits as shown in Word Address Byte

Requirements for Accessing the Write Protection Register.

Table 8-3. Word Address Byte Requirements for Accessing the Write Protection Register

A 7

A6

A5

A4

A3

A2

A1

A0

Write Protection Register

1

1

X

X

X

X

X

X

Following the word address byte are the contents of the 8-bit Write Protection register. The register format is shown

in Write Protection Register Format, and the WPR bit functions are included in Write Protection Register Bit Function.

Table 8-4. Write Protection Register Format

Operation

D7

D6

D5

D4

D3

D2

D1

D0

Read WPR

0

0

0

0

WPRE

WPB1

WPB0

WPRL

Write WPR

0

1

0: No Lock

0

1: Set Lock

Table 8-5. Write Protection Register Bit Function

Bit

Name

Type

Description

3

WPRE

Write Protection

Register Enable bit

R/W

0

No software write protection is enabled (Factory

Default).

1

Write protection is set by the state of the WPB[1:0] bits.

2-1

WPB[1:0] Write-Protect Block bits

R/W

00 Upper ¼ of EEPROM is write protected (Factory

Default).

01 Upper ½ of EEPROM is write protected.

10 Upper ¾ of EEPROM is write protected.

11 Entire EEPROM is write protected.

0

WPRL

Write-Protect Lock Bit

R/OTP

0

WPR can be written to; requires D5 = 0 during write

(Factory Default).

1

WPR will become permanently locked (requires

D5 = 1) during write.

• Write Protection Register Enable bit (WPRE), Bit 3

This bit is used to enable or disable the device software write protection feature. A logic ‘0’ in this position will

disable software write protection, and a logic ‘1’ will enable this function.

• Write-Protect Block bits (WPB[1:0]), Bits 2:1

These bits allow four levels of protection of the memory array provided that the WPRE bit is a logic ‘1’. If

the WPRE bit is a logic ‘0’, the state of the WPB[1:0] bits have no impact to device protection. The protected

address ranges are found in Table 8-6.

AT24CSW01X/AT24CSW02X

Write Protection

and its subsidiaries

Datasheet

DS20006396B-page 22