Figure 10-1. Serial Number Read

SCL

SDA

Start

by

Host

ACK

from

Client

ACK

from

Host

Device Address Byte

Word Address Byte

MSb

MSb

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

0

1

1

#

#

#

0

0

1

0

X

0

0

0

0

0

0

ACK

from

Host

NACK

from

Host

Stop

by

Host

ACK

from

Host

Device Address Byte

Serial Number Byte 80h

Serial Number Byte 8Fh

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

0

1

1

#

#

#

1

0 D7 D6 D5 D4 D3 D2 D1 D0 0

D7 D6 D5 D4 D3 D2 D1 D0

1

MSb

MSb

MSb

Dummy Write

Note:  # indicates the hardware address value which is managed by the ordering code of the device (see Table 6-2).

10.3

Write Operations in the Security Register

The Security register supports byte writes, page writes, and partial page writes in the upper 16 bytes of the region.

Page writes and partial page writes in the Security register have the same page boundary restrictions and behavior

as they do in the EEPROM region (see Write Operations).

Writing in the Security register requires beginning the device address byte with 1011b(Bh), matching the hardware

address bits (A2, A1, A0) to the corresponding value determined by the ordering code (see Table 6-2), and sending a

logic ‘0’ in the Read/Write Select bit. The device will ACK this sequence.

Following the device address byte, bits A7 and A6 of the word address byte must be set to 10b regardless of the

intended address being written. Refer to Table 6-3 for detailed requirements on these bits. Figure 10-2 is an example

of a byte write operation in the Security register.

Figure 10-2. Byte Write in the Security Register

SCL

SDA

Device Address Byte (Bh)

Word Address Byte

Data Word

Start

by

Host

ACK

from

Client

MSb

MSb

Stop

by

Host

MSb

1

2

3

4

5

6

7

8

9

1

0

1

1

#

#

#

0

0

1

2

3

4

5

6

7

8

9

D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

X A4 A3 A2 A1 A0 0

1

2

3

4

5

6

7

8

9

ACK

from

Client

ACK

from

Client

Note:  # indicates the hardware address value which is managed by the ordering code of the device (see Table 6-2).

The user-programmable portion of the Security register can be permanently inhibited from future writing with the Lock

command. The status of the Lock state can be determined by sending a subset of the Lock command.

10.3.1

Lock Command

The Lock command is an irreversible sequence that will permanently prevent all future writing to the Security register.

Once the Lock command has been executed, the Security register becomes read-only.

Note:  Once the Security register has been locked, it cannot be unlocked.

The Lock command protocol emulates a byte write operation to the Security register. However, the A7 through A4 bits

of the word address must be set to 0110b (6h). The remaining bits of the word address and the data word are “don’t

care” bits. Even though these bits are “don’t cares”, they still must be transmitted to the part. An ACK response to the

AT24CSW01X/AT24CSW02X

Security Register

and its subsidiaries

Datasheet

DS20006396B-page 28