AD9517-2ASLASHPCBZ datasheet(73/80 Pages) AD

73 / 80 page

Data Sheet

AD9517-2

Rev. F | Page 73 of 80

Reg.

Addr.

(Hex)

Bits

Name

Description

0x197

Divider 1 start high

Selects clock output to start high or start low.

0: starts low (default).

1: starts high.

[3:0]

Divider 1 phase offset

Phase offset (default = 0x0).

0x198

Divider 1 direct to output

Connects OUT2 and OUT3 to Divider 2 or directly to VCO or CLK.

0: OUT2 and OUT3 are connected to Divider 1 (default).

1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT2 and OUT3.

If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT2 and OUT3.

If Register 0x1E1[1:0] = 01b, there is no effect.

Divider 1 DCCOFF

Duty-cycle correction function.

0: enables duty-cycle correction (default).

1: disables duty-cycle correction.

Table 59. LVDS/CMOS Channel Dividers

Reg.

Addr.

(Hex)

Bits

Name

Description

0x199

[7:4]

Low Cycles Divider 2.1

Number of clock cycles (minus 1) of 2.1 divider input during which 2.1 output stays low.

A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).

[3:0]

High Cycles Divider 2.1

Number of clock cycles (minus 1) of 2.1 divider input during which 2.1 output stays high.

A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).

0x19A

[7:4]

Phase Offset Divider 2.2

Refer to LVDS/CMOS channel divider function description (default = 0x0).

[3:0]

Phase Offset Divider 2.1

Refer to LVDS/CMOS channel divider function description (default = 0x0).

0x19B

[7:4]

Low Cycles Divider 2.2

Number of clock cycles (minus 1) of 2.2 divider input during which 2.2 output stays low.

A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).

[3:0]

High Cycles Divider 2.2

Number of clock cycles (minus 1)of 2.2 divider input during which 2.2 output stays high.

A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).

0x19C

Bypass Divider 2.2

Bypasses (and powers down) 2.2 divider logic, routes clock to 2.2 output.

0: does not bypass (default).

1: bypasses.

Bypass Divider 2.1

Bypasses (and powers down) 2.1 divider logic, routes clock to 2.1 output.

0: does not bypass (default).

1: bypasses.

Divider 2 nosync

No sync.

0: obeys chip-level SYNC signal (default).

1: ignores chip-level SYNC signal.

Divider 2 force high

Forces Divider 2 output high. Requires that nosync also be set.

0: forces low (default).

1: forces high.

Start High Divider 2.2

Divider 2.2 start high/low.

0: starts low (default).

1: starts high.

Start High Divider 2.1

Divider 2.1 start high/low.

0: starts low (default).

1: starts high.

0x19D

Divider 2 DCCOFF

Duty-cycle correction function.

0: enables duty-cycle correction (default).

1: disables duty-cycle correction.

0x19E

[7:4]

Low Cycles Divider 3.1

Number of clock cycles (minus 1) of 3.1 divider input during which 3.1 output stays low.

A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).

[3:0]

High Cycles Divider 3.1

Number of clock cycles (minus 1) of 3.1 divider input during which 3.1 output stays high.

A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).

AD9517-2A/PCBZ Datenblatt(PDF) 73 Page - Analog Devices

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