AD9517-2ASLASHPCBZ datasheet(14/80 Pages) AD

14 / 80 page

AD9517-2

Data Sheet

Rev. F | Page 14 of 80

PD, SYNC, AND RESET PINS

Table 15.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

INPUT CHARACTERISTICS

These pins each have a 30 kΩ internal pull-up

resistor

Logic 1 Voltage

2.0

Logic 0 Voltage

0.8

Logic 1 Current

μA

Logic 0 Current

110

μA

Capacitance

RESET TIMING

Pulse Width Low

SYNC TIMING

Pulse Width Low

1.5

High speed

clock cycles

High speed clock is CLK input signal

LD, STATUS, AND REFMON PINS

Table 16.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

OUTPUT CHARACTERISTICS

When selected as a digital output (CMOS);

there are other modes in which these pins

are not CMOS digital outputs; see Table 54,

Output Voltage High (VOH)

2.7

Output Voltage Low (VOL)

0.4

MAXIMUM TOGGLE RATE

100

MHz

Applies when mux is set to any divider or

counter output or PFD up/down pulse; also

applies in analog lock detect mode; usually

debug mode only; beware that spurs may

couple to output when any of these pins are

toggling

ANALOG LOCK DETECT

Capacitance

On-chip capacitance; used to calculate RC

time constant for analog lock detect

readback; use a pull-up resistor

REF1, REF2, AND VCO FREQUENCY STATUS MONITOR

Normal Range

1.02

MHz

Frequency above which the monitor always

indicates the presence of the reference

Extended Range (REF1 and REF2 Only)

kHz

Frequency above which the monitor always

indicates the presence of the reference

LD PIN COMPARATOR

Trip Point

1.6

Hysteresis

260

AD9517-2A/PCBZ Datenblatt(PDF) 14 Page - Analog Devices

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