AT90USB646 datasheet(33/434 Pages) ATMEL

33 / 434 page

7593A–AVR–02/06

AT90USB64/128

Figure 5-9.

External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1(1)

Note:

1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or

SRW00 (lower sector).

The ALE pulse in period T7 is only present if the next instruction accesses the RAM (internal

or external).

5.5.6

External Memory Control Register A – XMCRA

• Bit 7 – SRE: External SRAM/XMEM Enable

Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8,

ALE, WR, and RD are activated as the alternate pin functions. The SRE bit overrides any pin

direction settings in the respective data direction registers. Writing SRE to zero, disables the

External Memory Interface and the normal pin and data direction settings are used.

• Bit 6..4 – SRL2:0: Wait-state Sector Limit

It is possible to configure different wait-states for different External Memory addresses. The

external memory address space can be divided in two sectors that have separate wait-state bits.

The SRL2, SRL1, and SRL0 bits select the split of the sectors, see Table 5-4 and Figure 5-4. By

default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external memory address

space is treated as one sector. When the entire SRAM address space is configured as one sec-

tor, the wait-states are configured by the SRW11 and SRW10 bits.

ALE

A15:8

Address

Prev. addr.

DA7:0

Address

Data

Prev. data

DA7:0 (XMBK = 0)

Data

Prev. data

Address

Data

Prev. data

Address

DA7:0 (XMBK = 1)

System Clock (CLKCPU)

Bit

7654

SRE

SRL2

SRL1

SRL0

SRW11

SRW10

SRW01

SRW00

XMCRA

Read/Write

R/W

Initial Value

0000

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