FEDL7732-01-10

OKI Semiconductor

MSM7732-01

8/29

SYNC

8 kHz synchronous signal input for transmit and receive PCM data.

Synchronize this signal with BCLK signal. Refer to Figure 2.

PCMOUT

Transmit PCM data output.

This PCM output signal is output from MSB synchronously with the rising edge of BCLK and SYNC. Refer to

Figure 2. This is a logic output pin so that external pull-up is not required. This pin outputs logic "L" except during

effective PCM data bits, and outputs logic "H" during power-down.

PCMIN

Receive PCM data input.

This PCM input signal is shifted in on the falling edge of BCLK and is input from MSB.

Refer to Figure 2.

Figure 2 PCM Interface Basic Timing Diagram

BCLK

SYNC

MSB

LSB

PCMIN or

PCMOUT

∗ 14 bit in the case of linear mode

8 kHz (125 µs)

(b) Short frame synchronous interface

8 kHz (125 µs)

BCLK

SYNC

MSB

LSB

PCMIN or

PCMOUT

∗ 14 bit in the case of linear mode

(a) Long frame synchronous interface