EV-RPG2-ECZ datasheet(5/21 Pages) AD

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Data Sheet

ADIN2299

SPECIFICATIONS

analog.com

Rev. 0 | 5 of 21

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Cycle Time

8 bytes of cyclic input and output data, Ethernet

applications processor interface

1 Guaranteed by design and characterization.

2 Cycle times vary based on protocol, link type, and application data.

TIMING CHARACTERISTICS

10 Mbps and 100 Mbps Ethernet MAC Interface Timing

Table 3 through Table 5 and Figure 2 through Figure 4 describe the Ethernet MAC applications processor, interface controller, timing

specifications. Note that the externally generated Ethernet MAC clock is fREFCLKEXT, and the internal system clock is fSYSCLK. To calculate the

externally generated Ethernet MAC clock timing and the internal system clock timing, use the following equations:

tREFCLKEXT = 1/fREFCLKEXT

tSYSCLK = 1/fSYSCLK

Table 3. 10 Mbps and 100 Mbps Ethernet MAC Reduced Media Independent Interface (RMII) Receive Signal Timing

Parameter

Min

Max

Unit

fREFCLKEXT

ETH0_REFCLK Frequency

MHz

tREFCLK

ETH0_REFCLK Period1

tREFCLKEXT – 1%

tREFCLKW

ETH0_REFCLK Width1

tREFCLKEXT × 35%

tREFCLKEXT × 65%

tREFCLKIS

Receive Input Valid to RMII ETH0_REFCLK Rising Edge (Data In Setup)

tREFCLKIH

RMII ETH0_REFCLK Rising Edge to Receive Input Invalid (Data In Hold)

2.0

1 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty-cycle variation or jitter.

Figure 2. RMII Receive Timing

Table 4. 10 Mbps and 100 Mbps Ethernet MAC RMII Transmit Signal Timing

Parameter

Min

Max

Unit

tREFCLKOV

RMII ETH0_REFCLK Rising Edge to Transmit Output Valid (Data Out Valid)

tREFCLKOH

RMII ETH0_REFCLK Rising Edge to Transmit Output Valid (Data Out Hold)

Figure 3. RMII Transmit Timing

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