Data Sheet

ADIN2299

SPECIFICATIONS

analog.com

Rev. 0 | 7 of 21

SPI Follower Interface Timing

Table 6 and Figure 5 describe the SPI port follower timing specifications. Note that, in SPI follower mode, the SPI clock is supplied externally

Table 6. SPI Port Follower Timing

Parameter

Min

Max

Unit

SPI0_CLK Frequency

10

MHz

SPI0_CLK High Period

ns

SPI0_CLK Low Period

ns

SPI0_CLK Period

ns

Last SPI0_CLK Edge to SPI0_SEL3_SS Not Asserted

5

ns

Sequential Transfer Delay

ns

SPI0_SEL3_SS Assertion to First SPI_CLK Edge

10.5

ns

Data Input Valid to SPI0_CLK Edge (Data Input Setup)

2

ns

SPI0_CLK Sampling Edge to Data Input Invalid

1.6

ns

SPI0_SEL3_SS Assertion to Data Out Active

0

14

ns

SPI0_SEL3_SS Deassertion to Data High Impedance

0

12.5

ns

SPI0_CLK Edge to Data Out Valid (Data Out Delay)

14

ns

SPI0_CLK Edge to Data Out Invalid (Data Out Hold)

0

ns

Figure 5. SPI Follower Timing