PCA8530DUGSLASHDAZ datasheet(22/103 Pages) NXP

22 / 103 page

PCA8530

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Product data sheet

Rev. 2 — 25 September 2014

22 of 103

NXP Semiconductors

PCA8530

Automotive 102 x 4 Chip-On-Glass LCD segment driver

8.6 Clock and frame frequency command

8.6.1 Oscillator

The internal logic and LCD drive signals of the PCA8530 are timed by the clock frequency

fclk, which is either internally generated by an on-chip oscillator circuit or externally

supplied.

The clock frequency fclk determines the internal data flow of the device that includes the

transfer of display data from the display RAM to the display segment outputs and the

generation of the LCD frame frequency.

8.6.2 External clock

When an external clock is used, the input pin OSC must be connected to VDD1. The clock

must be supplied to the CLK pin and must have an amplitude equal to the VDD1 voltage

supplied to the chip and be referenced to VSS1.

Remark: If an external clock is used, then this clock signal must always be supplied to the

device. Removing the clock may freeze the LCD in a DC state, which is not suitable for the

liquid crystal. Removal of the clock is possible when following the correct procedures as

described in Section 8.8.3 on page 29.

8.6.3 Internal clock

In applications where the internal clock is used, the input pin OSC must be connected to

VSS1. It is possible to make the clock frequency available on pin CLK by setting bit COE

logic 1 (see Table 10 on page 12). If pin CLK is not used, it should be left open. At

power-on the signal at pin CLK is disabled and pin CLK is in 3-state.

8.6.4 Command: Frame-frequency

With this command, the clock and frame frequency can be programmed when using the

internal clock.

The duty ratio of the clock output may change when choosing different values for the

frame frequency (see Table 24).

The LCD frame frequency is derived from the clock frequency by a fixed division (see

Equation 1).

(1)

Table 23.

Frame-frequency - frame frequency select command bit description

Bit

Symbol

Value

Description

-R/W

fixed value

RS[1:0]

fixed value

7 to 5

111

fixed value

4 to 0

FF[4:0]

see Table 24

clock and frame frequency (Hz)

clk

144

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