CS47L35 datasheet(69/300 Pages) CIRRUS

69 / 300 page

DS1085F3

CS47L35

4.3 Digital Core

When the PWMn_OVD bit is set, the duty cycle of the respective PWM generator is set to a fixed ratio; in this case, the

duty cycle ratio is configurable using the PWMn_LVL fields.

The PWM generator clock frequency is selected using PWM_CLK_SEL. For best performance, the highest available

setting should be used. Note that the PWM generator clock must not be set to a higher frequency than SYSCLK.

The CS47L35 automatically checks to confirm that the SYSCLK frequency is high enough to support the digital mixer

paths. If an attempt is made to enable a PWM signal mixer path, without sufficient SYSCLK cycles to support it, the attempt

fails. Note that any signal paths that are already active are not affected under such circumstances.

The status bits in registers R1600–R2936 indicate the status of each of the digital mixers. If an underclocked error

condition occurs, these bits indicate which mixers have been enabled.

4.3.13 Sample-Rate Control

The CS47L35 supports multiple signal paths through the digital core. Stereo full-duplex sample-rate conversion is provided

to allow digital audio to be routed between interfaces operating at different sample rates.

The master clock reference for the audio signal paths is SYSCLK, as described in Section 4.16. Every digital signal path

must be synchronized to SYSCLK.

Up to three different sample rates may be in use at any time on the CS47L35; all of these sample rates must be

synchronized to SYSCLK.

Sample-rate conversion is required when routing any audio path between digital functions that are configured for different

sample rates.

Table 4-20. PWM Generator Control

Bit

Label

Default

Description

R48 (0x0030)

PWM_Drive_1

10:8 PWM_CLK_

SEL[2:0]

000

PWM Clock Select

000 = 6.144 MHz (5.6448 MHz)

001 = 12.288 MHz (11.2896 MHz)

010 = 24.576 MHz (22.5792 MHz)

All other codes are reserved.

The frequencies in brackets apply for 44.1 kHz–related sample rates only.

PWM_CLK_SEL controls the resolution of the PWM generator; higher settings

correspond to higher resolution.

The PWM Clock must be less than or equal to SYSCLK.

PWM2_OVD

PWM2 Generator Override

0 = Disabled (PWM duty cycle is controlled by audio source)

1 = Enabled (PWM duty cycle is controlled by PWM2_LVL).

PWM1_OVD

PWM1 Generator Override

0 = Disabled (PWM1 duty cycle is controlled by audio source)

1 = Enabled (PWM1 duty cycle is controlled by PWM1_LVL).

PWM2_ENA

PWM2 Generator Enable

0 = Disabled

1 = Enabled

PWM1_ENA

PWM1 Generator Enable

0 = Disabled

1 = Enabled

R49 (0x0031)

PWM_Drive_2

9:0 PWM1_LVL[9:0]

0x100

PWM1 Override Level. Sets the PWM1 duty cycle when PWM1_OVD = 1.

Coded as 2’s complement.

0x000 = 50% duty cycle

0x200 = 0% duty cycle

R50 (0x0032)

PWM_Drive_3

9:0 PWM2_LVL[9:0]

0x100

PWM2 Override Level. Sets the PWM2 duty cycle when PWM2_OVD = 1.

Coded as 2’s complement.

0x000 = 50% duty cycle

0x200 = 0% duty cycle

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