CS47L35 datasheet(34/300 Pages) CIRRUS

34 / 300 page

DS1085F3

CS47L35

4.2 Input Signal Path

The input signal paths are muted by default. It is recommended that deselecting the mute should be the final step of the

path enable control sequence. Similarly, the mute should be selected as the first step of the path-disable control sequence.

The input signal path mute functions are controlled using the bits described in Table 4-4.

The MICVDD power domain must be enabled when using the analog input signal paths. This power domain is provided

using an internal charge pump (CP2) and LDO regulator (LDO2). See Section 4.19 for details of these circuits.

The system clock, SYSCLK, must be configured and enabled before any audio path is enabled. The input signal paths

should be kept disabled (INnx_ENA = 0) if SYSCLK is not enabled. The 32-kHz clock may also be required, depending on

the path configuration. See Section 4.16 for details of the system clocks (including requirements for reconfiguring SYSCLK

while audio paths are enabled).

The CS47L35 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the input signal

paths and associated ADCs. If the frequency is too low, an attempt to enable an input signal path fails. Note that active

signal paths are not affected under such circumstances.

The status bits in Register R769 indicate the status of each of the input signal paths. If an underclocked error condition

occurs, these bits indicate which input signal paths have been enabled.

4.2.5

Input Signal Path Sample-Rate Control

The input signal paths may be selected as input to the digital mixers or signal-processing functions within the CS47L35

digital core. The sample rate for the input signal paths is configured using IN_RATE; see Table 4-21.

Note that sample-rate conversion is required when routing the input signal paths to any signal chain that is configured for

a different sample rate.

4.2.6

Input Signal Path Configuration

The CS47L35 supports up to six analog inputs or up to four digital inputs. Selectable combinations of analog (mic or line)

and digital inputs are multiplexed into two stereo input signal paths.

Table 4-2. Input Signal Path Enable

Bit

Label

Default

Description

R768 (0x0300)

Input_Enables

IN2L_ENA

Input Path 2 (left) enable

0 = Disabled

1 = Enabled

IN2R_ENA

Input Path 2 (right) enable

0 = Disabled

1 = Enabled

IN1L_ENA

Input Path 1 (left) enable

0 = Disabled

1 = Enabled

IN1R_ENA

Input Path 1 (right) enable

0 = Disabled

1 = Enabled

R769 (0x0301)

Input_Enables_Status

IN2L_ENA_STS

Input Path 2 (left) enable status

0 = Disabled

1 = Enabled

IN2R_ENA_STS

Input Path 2 (right) enable status

0 = Disabled

1 = Enabled

IN1L_ENA_STS

Input Path 1 (left) enable status

0 = Disabled

1 = Enabled

IN1R_ENA_STS

Input Path 1 (right) enable status

0 = Disabled

1 = Enabled

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