Data Sheet

LT7200S

analog.com

Rev 0

26 of 35

2. Are COUT and L closely connected? The (–) plate of COUT returns current to GND and the (–) plate of CIN.

3. Place the FB dividers close to the part with kelvin connections to VOUT and GND at the point of load.

4. Keep sensitive components away from the SW pin. Route the FB resistors, RT resistor, compensation component,

and INTVCC bypass caps away from the SW trace and inductor.

5. A ground plane is preferred.

6. Flood all unused areas on all layers with copper, which reduces the temperature rise of power components.

Connect these copper areas to GND.

Figure 38. Example of Top Layer PCB Design

Design Example

As a design example, consider the LT7200S in an application with the following specifications:

VIN = 12V

VOUT = 1.2V

IOUT(MAX) = 5A

fSW = 1MHz

First, to program the output to 1.2V, set RFB1 to be 10kΩ and RFB2 to be 14kΩ, typical values that can be used here for

both resistors is 10kΩ. For best accuracy, use a 0.1% resistor.

For a typical soft start time of 2ms (0% to 100% of final VOUT value), the CTRACK should be:

5μA = CSS x

0.5V

2ms

31.2mm × 18.5mm

31.2mm × 18.5mm