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LTC3314AACBZ-R7 Datenblatt(PDF) 10 Page - Analog Devices |
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LTC3314AACBZ-R7 Datenblatt(HTML) 10 Page - Analog Devices |
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10 / 26 page ![]() LTC3314A 10 Rev. 0 For more information www.analog.com PIN FUNCTIONS PVIN1 (Leads A1, A2): Input Supply for Buck Regulator 1. Supplies gate drive circuits and inductor current when the high side turns on. Bypass PVIN1 to PGND with a separate low ESR capacitor close to the pins. PVIN1 and PVIN2 should be shorted externally. Use separate capaci- tors to PGND for PVIN1 and PVIN2 to prevent interaction between the buck regulators. There is an internal 20Ω resistor from PVIN1 to AVIN to help create a filtered supply for the internal control circuits. SW1 (Leads A3, B1, B2, B3): Switch Node for Buck Regulator 1. Connect an external inductor to this pin. BST1 (Lead A4): Internal supply for high side gate drive circuits for Buck 1. Connect a 22nF capacitor from SW1 to BST1 close to the pins. FB1 (Lead A5): Feedback Input for Buck Regulator 1. Program the output voltage of Buck 1 by connecting this pin to the middle node of a resistor divider between the output and ground. The FB1 pin is regulated to 500mV. A phase lead capacitor connected between VOUT1 and FB1 may be used to optimize transient response. PGOOD1 (Lead B4): Power Good (Open-Drain) Output for Buck Regulator 1. When the regulated output voltage is outside the power-good voltage window, and PVIN is above 2.25V, this pin is driven LOW. The PGOOD1 output is also pulled low when PVIN is above 2.25V and Buck Regulator 1 is in shutdown. EN1 (Lead B5): Active High Enable Input for Buck Regulator 1. The EN1 pin has a precision threshold. An external resistor divider from VIN, or from another sup- ply, can be used to program when Buck Regulator 1 is enabled. If the enable function is not required, tie EN1 directly to AVIN. The EN1 pin should not be floated. PGND (Leads C1, C2, C3, D1, D2, D3): The PGND pins are the return path of the internal bottom side switches. Connect the PGND leads together. Connect the negative terminals of the input capacitors as close to the PGND pins as possible. The PGND node is the main thermal highway and should be connected to a large PCB ground plane with many large vias. RT (Lead C4): The RT pin sets the switching frequency with an external resistor to AGND. If this pin is tied to AVIN, the buck will switch at the default oscillator fre- quency. If an external clock is driving the MODE/SYNC pin, the RT pin is ignored. AVIN (Lead C5): Filtered input supply used to bias the internal bandgap reference and buck control circuits. There are internal 20Ω resistors from PVIN1 to AVIN, and from PVIN2 to AVIN. Connect a 1µF ceramic capacitor from AVIN to AGND to provide a filtered supply for the internal control circuits. Do not externally load this pin. MODE/SYNC (Lead D4): Mode Selection and External Clock Synchronization Input. Ground this pin to enable pulse-skipping mode. Tie this pin to AVIN to enable Burst Mode operation for higher efficiency at light loads. Float this pin to enable forced continuous mode for fast tran- sient response and full frequency operation over a wide load range. Drive MODE/SYNC with an external clock to synchronize both switchers to the applied frequency. The slope compensation is automatically adapted to the exter- nal clock frequency. In the absence of an external clock, the RT pin controls the switching frequency. AGND (Lead D5): The AGND pin is the ground pin for the internal bias circuits, including the bandgap refer- ence. Connect the bottom resistor of the FB1 and FB2 resistor dividers to the AGND pin for accurate output voltage regulation. SW2 (Leads E1, E2, E3, F3): Switch Node for Buck Regulator 2. Connect an external inductor to this pin. PGOOD2 (Lead E4): Power Good (Open-Drain) Output for Buck Regulator 2. When the regulated output voltage is outside the power-good voltage window, and PVIN is above 2.25V, this pin is driven LOW. The PGOOD2 output is also pulled low when PVIN is above 2.25V and Buck Regulator 2 is in shutdown. |
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