LTC3314AACBZ-R7 datasheet(21/26 Pages) AD

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LTC3314A

Rev. 0

For more information www.analog.com

PCB Layout Considerations

The LTC3314A is a high-performance IC designed for high

efficiency and fast transient response. For optimal results

carefully consider the layout of the PCB board and follow

the recommendations below to ensure proper operation.

See Figure 3 for a recommended PCB layout.

1. Connect the PGND pin (Leads C1, C2, C3, D1, D2, D3)

directly to a large, unbroken ground plane under the

application circuit on the layer closest to the surface

layer to minimize thermal and electrical impedance.

Additionally, connect the PGND leads to the PVIN1

and PVIN2 decoupling capacitors on the top layer with

short, wide traces.

2. The PVIN1 (Leads A1, A2) and PVIN2 (Leads F1, F2)

input supply leads should have local decoupling

capacitors with the ground side of the capacitors con-

nected on the top layer to the ground plane close to

the PGND leads. These capacitors provide the AC cur-

rent to the internal power MOSFETs and their drivers.

Large, switched currents flow in these capacitors and

it is important to minimize inductance from these

capacitors by choosing a small case size, such as

0603, and placing them close to the leads on the top

side of the board. To further minimize inductance and

input noise, smaller 0201 capacitors can be placed in

parallel, also as close as possible to the leads, from

PVIN1 to PGND and from PVIN2 to PGND.

3. Place both regulator inductors on the same side of the

board as the LTC3314A. The switching power traces

connecting SW1 (Leads A3, B1, B2, B3) and SW2

(Leads E1, E2, E3, F3) to their inductors should be

minimized to reduce radiated EMI and parasitic cou-

pling. Due to the large voltage swing on the switching

nodes, high impedance sensitive nodes, such as the

feedback nodes, should be kept far away or shielded

from SW1 and SW2. Minimize the trace lengths from

the inductors to their output capacitors.

APPLICATIONS INFORMATION

COUT1

COUT2

CFF1

CFF2

RB1 RA1 RT

RA2 RB2

CVIN

CIN1

CIN2

CBST1

CBST2

VOUT1

VIN

VOUT2

GROUND PLANE ON LAYER 2

3314A F03

AGND

Figure 3. Recommended PCB Layout

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