HC05V7GRSSLASHD datasheet(39/170 Pages) NXP

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SECTION 4: CPU CORE

Page 25

MC68HC05V7 Specification Rev. 1.0

SECTION 4

CPU CORE

The MC68HC05V7 has a 16K memory map. Therefore it uses only the lower 14 bits of the

address bus. In the following discussion the upper 2 bits of the address bus can be ignored.

Also, the STOP instruction may be selected to act as either the normal STOP instruction or

pull a reset by means of a mask option. All other instructions and registers behave as

described in this chapter.

4.1

REGISTERS

The MCU contains five registers that are hard-wired within the CPU and are not part of the

memory map. These five registers are shown in Figure 4-1 and are described in the

following paragraphs.

Figure 4-1:

MC68HC05 Programming Model

4.1.1

ACCUMULATOR (A)

The accumulator is a general purpose 8-bit register, as shown in Figure 4-1. The CPU uses

the accumulator to hold operands and results of arithmetic calculations or nonarithmetic

operations. The accumulator is unaffected by a reset of the device.

4.1.2

INDEX REGISTER (X)

The index register shown in Figure 4-1 is an 8-bit register that can perform two functions:

•

Indexed addressing

•

Temporary storage

CONDITION CODE REGISTER

ACCUMULATOR

INDEX REGISTER

STACK POINTER

111

PROGRAM COUNTER

NZC

HALF-CARRY BIT (FROM BIT 3)

INTERRUPT MASK

NEGATIVE BIT

ZERO BIT

CARRY BIT

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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