HC05V7GRSSLASHD datasheet(40/170 Pages) NXP

40 / 170 page

SECTION 4: CPU CORE

Page 26

MC68HC05V7 Specification Rev. 1.0

In indexed addressing with no offset, the index register contains the low byte of the operand

address, and the high byte is assumed to be $00. In indexed addressing with an 8-bit offset,

the CPU finds the operand address by adding the index register contents to an 8-bit

immediate value. In indexed addressing with a 16-bit offset, the CPU finds the operand

address by adding the index register contents to a 16-bit immediate value

The index register can also serve as an auxiliary accumulator for temporary storage. The

index register is unaffected by a reset of the device.

4.1.3

STACK POINTER (SP)

The stack pointer shown in Figure 4-1 is a 16-bit register internally. In devices with memory

maps less than 64 Kbytes the unimplemented upper address lines are ignored. The stack

pointer contains the address of the next free location on the stack. During a reset or the

reset stack pointer (RSP) instruction, the stack pointer is set to $00FF. The stack pointer is

then decremented as data is pushed onto the stack and incremented as data is pulled from

the stack.

When accessing memory, the ten most significant bits are permanently set to 0000000011.

The six least significant register bits are appended to these ten fixed bits to produce an

address within the range of $00FF to $00C0. Subroutines and interrupts may use up to 64

($40) locations. If 64 locations are exceeded, the stack pointer wraps around and writes

over the previously stored information. A subroutine call occupies two locations on the

stack and an interrupt uses five locations.

4.1.4

PROGRAM COUNTER (PC)

The program counter shown in Figure 4-1 is a 16-bit register internally. In devices with

memory maps less than 64 Kbytes the unimplemented upper address lines are ignored.

The program counter contains the address of the next instruction or operand to be fetched.

Normally, the address in the program counter increments to the next sequential memory

location every time an instruction or operand is fetched. Jump, branch, and interrupt

operations load the program counter with an address other than that of the next sequential

location.

4.1.5

CONDITION CODE REGISTER (CCR)

The CCR shown in Figure 4-1 is a 5-bit register in which four bits are used to indicate the

results of the instruction just executed. The fifth bit is the interrupt mask. These bits can be

individually tested by a program, and specific actions can be taken as a result of their state.

The condition code register should be thought of as having three additional upper bits that

are always ones. Only the interrupt mask is affected by a reset of the device. The following

paragraphs explain the functions of the lower five bits of the condition code register.

4.1.5.1

Half Carry Bit (H-Bit)

When the half-carry bit is set, it means that a carry occurred between bits 3 and 4 of the

accumulator during the last ADD or ADC (add with carry) operation. The half-carry bit is

required for binary-coded decimal (BCD) arithmetic operations.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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