HC05V7GRSSLASHD datasheet(69/170 Pages) NXP

69 / 170 page

SECTION 7: POWER SUPPLY AND REGULATION

Page 55

MC68HC05V7 Specification Rev. 1.0

The effect of not connecting the two VDD pins together is under evaluation and it is recom-

mended that they be connected at this time.

2) VDD to VSSD (pins 3 & 4): MCU internal digital power decoupling. These pins are

connected to the on-chip regulator output via a small resistance. Decouple with a 0.1uF

ceramic or polystyrene capacitator. If the self-resonance frequency of the decoupling cir-

cuit (assume 4nH per bond wire) is too low, add a 0.01uF or smaller capacitor in parallel to

increase the bandwidth of the decoupling network. Ensure the smaller capacitor is located

closest to the VDD and VSSD pins.

3) VCCA to VSSA1 and VSSA2: Analog subsystem power supply pins. These pins are

internally isolated from the digital VDD and VSS supplies. The VSSA1 pin provides a ground

return for the A/D subsystem. The VSSA2 pin provides a ground return for the DLC sub-

system. The analog supply pins should be appropriately ﬁltered to prevent any external

noise effecting the analog subsystems. The VSSA1 and VSSA2 pins should be brought

together with the digital ground at a single point which has a low (HF) impedance to

ground to prevent common mode noise problems. If this is not practical, then the VSSA1

and VSSA2 printed circuit board (PCB) traces should be routed in such a manner that digi-

tal ground return current is impeded from passing through the analog input ground refer-

ence as shown in the single sided PCB example below.

SSD

SSA

ANx

To System GND

AIN

SSD

SSA

ANx

AGND

AIN

GND

Shielded cable,

GND

Shielded cable, Twisted pair, etc.

Poor Analog Grounding

Better Analog Grounding

Twisted pair, etc.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC05V7GRS/D Datenblatt(PDF) 69 Page - NXP Semiconductors