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HC05V7GRS/D Datenblatt(PDF) 109 Page - NXP Semiconductors |
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HC05V7GRS/D Datenblatt(HTML) 109 Page - NXP Semiconductors |
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109 / 170 page ![]() SECTION 15: MESSAGE DATA LINK CONTROLLER Page 95 MC68HC05V7 Specification Rev. 1.0 15.2 MDLC CPU INTERFACE 15.2.1 OUTLINE The CPU Interface provides the interface between the CPU and the MDLC. It consists of 4 user registers. A full description of each register follows: Physical Interface To CPU Protocol Handler MUX Interface CPU Interface Rx/Tx Buffers To J1850 Bus MDLC Figure 15-2: MDLC User Registers Name Addr MCR MSR MTCR MRSR $000E $000F $0010 $0011 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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