AT25DF021A datasheet(35/59 Pages) RENESAS

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DS-AT25DF021A-042 Rev. J

Page 35

12/22/22

AT25DF021A Datasheet

11.3 Write Status Register

The Write Status Register command is used to modify the SPRL bit of the Status Register and/or to perform a

Global Protect or Global Unprotect operation. Before the Write Status Register command can be issued, the Write

Enable command must have been previously issued to set the WEL bit in the Status Register to a logical 1.

To issue the Write Status Register command, the CS pin must first be asserted and the opcode of 01h must be

clocked into the device followed by one byte of data. The one byte of data consists of the SPRL bit value, a don’t

care bit, four data bits to denote whether a Global Protect or Unprotect must be performed, and two additional

don’t care bits (see Table 11). Any additional data bytes that are sent to the device are ignored. When the CS pin

is deasserted, the SPRL bit in the Status Register is modified, and the WEL bit in the Status Register is reset back

to a logical 0. The values of bits 5, 4, 3, and 2 and the state of the SPRL bit before the Write Status Register

command was executed (the prior state of the SPRL bit) determines whether or not a Global Protect or Global

Unprotect is performed. Please refer to the “Global Protect/Unprotect” on page 25 for more details.

The complete one byte of data must be clocked into the device before the CS pin is deasserted; otherwise, the

device aborts the operation, the state of the SPRL bit does not change, no potential Global Protect or Unprotect is

performed, and the WEL bit in the Status Register is reset back to the logical 0 state.

If the WP pin is asserted, then the SPRL bit can only be set to a logical 1. If an attempt is made to reset the SPRL

bit to a logical 0 while the WP pin is asserted, then the Write Status Register command is ignored, and the WEL bit

in the Status Register is reset back to the logical 0 state. In order to reset the SPRL bit to a logical 0, the WP pin

must be deasserted.

Figure 28. Write Status Register

Table 11. Write Status Register Format

Bit 7

Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

SPRL

Global Protect/Unprotect

SCK

MSB

0000000

410 11

814 15

OPCODE

MSB

DDDD

STATUS REGISTER IN

High-Impedance

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