AT25DF021A datasheet(7/59 Pages) RENESAS

7 / 59 page

DS-AT25DF021A-042 Rev. J

Page 7

12/22/22

AT25DF021A Datasheet

Pin Descriptions and Pinouts

Table 1. Pin Descriptions

Symbol

Name and Function

Asserted

State

Type

CHIP SELECT

Asserting the CS pin selects the device. When the CS pin is deasserted, the device is

deselected and normally be placed in standby mode (not Deep Power-Down mode), and the

SO pin is in a high-impedance state. When the device is deselected, data is not accepted on

the SI pin.

A high-to-low transition on the CS pin is required to start an operation, and a low-to-high

transition is required to end an operation. When ending an internally self-timed operation such

as a program or erase cycle, the device does not enter the standby mode until the completion

of the operation.

Low

Input

SCK

SERIAL CLOCK

This pin is used to provide a clock to the device and is used to control the flow of data to and

from the device. Command, address, and input data present on the SI pin is always latched in

on the rising edge of SCK, while output data on the SO pin is always clocked out on the falling

edge of SCK.

Input

SI (I/O0)

SERIAL INPUT

The SI pin is used to shift data into the device. The SI pin is used for all data input including

command and address sequences. Data on the SI pin is always latched in on the rising edge of

SCK.

With the Dual-Output Read commands, the SI Pin becomes an output pin (I/O0) in conjunction

with other pins to allow two bits of data on (I/O1-0) to be clocked out on every falling edge of

SCK.

To maintain consistency with the SPI nomenclature, the SI (I/O0) pin is referenced as the SI pin

unless specifically addressing the Dual-I/O modes in which case it is referenced as I/O0.

Data present on the SI pin is ignored whenever the device is deselected (CS is deasserted).

Input/

Output

(I/O1)

SERIAL OUTPUT

The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out

on the falling edge of SCK.

With the Dual-Output Read commands, the SO Pin remains an output pin (I/O1) in conjunction

with other pins to allow two bits of data on (I/O1-0) to be clocked out on every falling edge of

SCK.

To maintain consistency with the SPI nomenclature, the SO (I/O1) pin is referenced as the SO

pin unless specifically addressing the Dual-I/O modes in which case it is referenced as I/O1.

The SO pin is in a high-impedance state whenever the device is deselected (CS is deasserted).

Input/

Output

WRITE PROTECT

The WP pin controls the hardware locking feature of the device. Please refer to “Protection

Commands and Features” on page 23 for more details on protection features and the WP pin.

The WP pin is internally pulled-high and may be left floating if hardware controlled protection is

not used. However, it is recommended that the WP pin also be externally connected to VCC

whenever possible.

Low

Input

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