STUW81300 datasheet(23/63 Pages) STMICROELECTRONICS

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DS11314 Rev 7

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STuW81300

Circuit description

7.1

Reference input stage

The reference input stage supports the use of different modes for the reference clock signal.

Both single-ended and differential modes (LVDS, LVECPL) are supported; a crystal mode is

also provided in order to build a Pierce type crystal oscillator. Figure 22 shows the

connections required for the supported configurations.

In single-ended and differential modes, the inputs must be AC coupled as the REF_CLKP

and REF_CLKN pins are internally biased to an optimal DC operating point. The best

phase-noise performance is obtained for signals with a high slew rate, such as a square

wave.

Figure 22. Reference clock buffer configurations: single-ended (A),

differential (B), crystal mode (C)

7.2

Reference divider

The 13-bit programmable reference counter divides the input reference frequency to the

desired PFD frequency. The division ratio is programmable from 1 to 8191.

The maximum allowable input frequency of the R-Counter is 200 MHz.

The reference clock frequency can be extended up to 400 MHz by enabling the divide-by-2

stage or up to 800 MHz by enabling the divide-by-4 stage.

A frequency doubler is provided in order to double low reference frequencies and increase

the PFD operating frequency, thus allowing easier filtering of the out-of-band noise of the

Delta-Sigma Modulator. The doubler introduces a noise degradation in the in-band PLL

noise, so this feature should be used with care.

When the doubler is enabled, the maximum reference clock frequency is limited to 25 MHz,

leading to a maximum PFD frequency of 50 MHz.

MSv43272V1

STUW81300 Datenblatt(PDF) 23 Page - STMicroelectronics