STUW81300 datasheet(42/63 Pages) STMICROELECTRONICS

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Circuit description

STuW81300

42/63

DS11314 Rev 7

[12] VCALB_MODE: VCO calibrator mode selection.

Settings for VCO core supplied at 4.5 V:

0: Mandatory for FVCO ≤ 4500 MHz

1: Mandatory for FVCO > 4500 MHz

Settings for VCO core supplied at 3.3 V:

0: Not allowed

1: Mandatory for the whole FVCO range

[11] KVCO_COMP_DIS: disable KVCO compensation circuit

0: compensation enabled (default - CP current auto-adjusted to compensate KVCO variation)

1: compensation disabled (CP current fixed by CP_SEL settings)

[10] PFD_POL: set PFD polarity

0: standard mode (default)

1: “inverted” mode (to be used only with active inverting loop filter or with VCO with negative

tuning characteristics)

[9:8] REF_BUFF_MODE: set reference clock buffer mode

00: (0) Reserved

01: (1) Differential Mode (reference clock signal on pin #20 and #21)

10: (2) XTAL Mode (Xtal oscillator enabled with crystal connected on pin #20 and #21)

11: (3) Single Ended Mode (Ref. clock signal on pin #21)

[7] MUTE_LOCK_EN: enables mute function

0: “mute on unlock” function disabled

1: “mute on unlock” function enabled (RF output stages are put OFF when PLL is unlocked)

[6] LD_ACTIVELOW: set low state as lock indicator

0: set lock indicator active high (LD=0 means PLL unlocked; LD=1 means PLL locked)

1: set lock indicator active low (LD=0 means PLL locked; LD=1 means PLL unlocked)

[5:3] LD_PREC: set lock detector precision

000: (0) 2 ns (default for integer mode)

001: (1) 4 ns (default for fractional mode)

010: (2) 6 ns

011: (3) 8 ns

100: (4) 10 ns

101: (5) 12 ns

110: (6) 14 ns

111: (7) 16 ns

[2:0] LD_COUNT: set lock detector counter for lock condition

000: (0) 4

001: (1) 8 (default for FPFD ~1 MHz in integer mode)

010: (2) 16

011: (3) 64

100: (4) 256

101: (5) 1024 (default for FPFD ~50 MHz in both fractional/integer mode)

110: (6) 2048

111: (7) 4096

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