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STUW81300 Datenblatt(PDF) 40 Page - STMicroelectronics |
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STUW81300 Datenblatt(HTML) 40 Page - STMicroelectronics |
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40 / 63 page ![]() Circuit description STuW81300 40/63 DS11314 Rev 7 [16:15] PFD_DEL_MODE: set PFD delay mode; delay values set by PFD_DEL[1:0] in register ST0 00: (0) no delay (default) 01: (1) VCO_DIV delayed 10: (2) REF_DIV delayed 11: (3) Reserved [14:13] REF_PATH_SEL: reference clock path selection 00: (0) Direct 01: (1) Doubled in single mode; Not Applicable in differential mode 10: (2) Divided by 2 11: (3) Divided by 4 [12:0] R: set Reference clock divider ratio (allowed setting range 1 to 8191) |
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