ISL81601 datasheet(36/54 Pages) RENESAS

36 / 54 page

FN9299 Rev.3.1

Page 36 of 53

May 27, 2021

ISL81601

5. Functional Description

In Burst mode, an internal window comparator takes control of the output voltage. The comparator monitors the

FB_OUT pin voltage. When the FB_OUT pin voltage is higher than 0.82V, the controller enters Low Power Off

mode. Some of the unnecessary internal circuitries are powered off. When the FB_OUT pin voltage drops to 0.8V,

the controller wakes up and runs in a fixed level peak current controlled D/(1-D) Buck-Boost mode when

VIN -VOUT < 2V and Buck mode when VIN -VOUT > 2V. In the D/(1-D) Buck-Boost mode, Q1 and Q3 conduct in

D*T period, where D is the duty cycle and T is the switching period. Q2 and Q4 complimentarily conduct in

(1-D)*T period. Q1 and Q3 are turned on by the clock signal and turned off when inductor current rises to the level

that the input current sense op amp input voltage reaches VBST-CS, typical 27mV. After Q1 and Q3 are turned off,

Q2 and Q4 are turned on to pass the energy stored in the inductor to the output until next cycle begins. The output

voltage increases in the wake up period. When the output reaches 0.82V again, the controller enters into Low

Power Off mode again. When the load current increases, the Low Power Off mode period decreases. When the off

mode period disappears and the load current further increases but still does not meet the Equation 13 exit condition,

the output voltage drops. When the FB_OUT pin voltage drops to 0.78V, the controller exits Burst mode and runs

in normal DE PWM mode. The voltage error amplifier takes control of the output voltage regulation.

In Low Power Off mode, the CLKEN pin goes low. By connecting the BSTEN and CLKEN pins together in a

multiple chip parallel system, the Burst mode enter/exit and burst on/off control are all synchronized.

Because the VOUT is controlled by a window comparator in Burst mode, higher than normal low frequency voltage

ripples appears on the VOUT, which can generate audible noise if the inductor and output capacitors are not chosen

properly. Also, the efficiency in D/(1-D) Buck-Boost mode is low. To avoid these drawbacks, the Burst mode can

be disabled by choosing a bigger RIM_OUT to set the IMON_OUT pin voltage higher than 0.88V at no load

condition, shown in Equation 14. The part runs in DE mode only. Pulse Skipping mode can also be implemented to

lower the light load power loss with much lower output voltage ripple as the VOUT is always controlled by the

regulator Gm1.

5.8

Prebiased Power-Up

The ISL81601 can soft-start with a prebiased output by running in forced DE mode during soft-start. The output

voltage is not pulled down during prebiased start-up. The PWM mode is not active until the soft-start ramp reaches

90% of the output voltage times the resistive divider ratio. Forced DE mode is set again when the SS/TRK pin

voltage is pulled to less than 0.3V by either internal or external circuit.

The overvoltage protection function is still alive during soft-start of the DE mode operation.

RIM_OUTxISENOFFSET vIMONOUTBSTEX



(EQ. 14)

ISL81601 Datenblatt(PDF) 36 Page - Renesas Technology Corp