2

105 Hardware Specifications

Preliminary/Subject to Change without Notice

1.1 MPC105 Overview

The MPC105 provides a PowerPC reference platform-compliant bridge between PowerPC 601

™,

PowerPC 603

™, and PowerPC 604™ microprocessors and the PCI bus. PCI support allows system

designers to rapidly design systems using peripherals already designed for PCI and the other standard

interfaces available in the personal computer hardware environment. The MPC105 integrates secondary

cache control and a high-performance memory controller that supports DRAM, synchronous DRAM

(SDRAM), ROM, and Flash ROM. The MPC105 uses an advanced, 3.3 V CMOS process technology and

is fully compatible with TTL devices.

The MPC105 supports a programmable interface to a variety of PowerPC microprocessors operating at

various bus speeds. The MPC105’s 60x interface allows for a variety of system configurations by providing

support for either a second processor or a secondary (L2) cache. The L2 cache control unit generates the

arbitration and support signals necessary to maintain a write-through or write-back lookaside cache.

The MPC105’s PCI interface is designed to connect the processor and memory system to the PCI local bus

without the need for “glue” logic. The MPC105 acts as both a master and slave device on the PCI bus.

The memory interface controls processor and PCI interactions to main memory. It is capable of supporting

a variety of DRAM or SDRAM, and ROM or Flash ROM configurations.

The MPC105 provides hardware support for four levels of power reduction—nap, doze, sleep, and suspend.

The MPC105’s design is fully static, allowing internal logic states to be preserved during all power saving

modes.

1.1.1 MPC105 Features

Major features of the MPC105 are as follows:

•

Processor interface

— 60x processors supported at a wide range of frequencies

— 32-bit address bus

— Configurable 64- or 32-bit data bus

— Accommodates an upgrade of either an external L2 cache or a secondary processor

— Arbitration for secondary processor on-chip

— Full memory coherency supported

— Pipelining of 60x accesses

— Store gathering on 60x-to-PCI writes

•

Secondary (L2) cache control

— Configurable for write-through or write-back operation

— 256K, 512K, 1M sizes

— Up to 4 Gbytes of cacheable space

— Direct-mapped

— Parity supported

— Supports external byte decode or on-chip byte decode for write enables

— Programmable timing supported

— Synchronous burst and asynchronous SRAMs supported

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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