6

105 Hardware Specifications

Preliminary/Subject to Change without Notice

Figure 1. SYSCLK Input Timing Diagram

1.3.2.2 Input AC Specifications

Table 6 provides the input AC timing specifications for the MPC105 as defined in Figure 2 and Figure 3.

These specifications are for operation between 16.67 and 33.33 MHz bus clock (SYSCLK) frequencies.

Table 5. Clock AC Timing Specifications

Vdd = 3.3

± 5% Vdc, GND = 0 Vdc

Num

Characteristic

Min

Max

Unit

Notes

Frequency of operation

16.67

33.33

MHz

1

SYSCLK cycle time

30.0

60.0

ns

2,3

SYSCLK rise and fall time

—

2.0

ns

1

4

SYSCLK duty cycle measured at 1.4 V

40.0

60.0

%

5a

SYSCLK pulse width high measured at 1.4 V

12

18

ns

2

5b

SYSCLK pulse width low measured at 1.4 V

12

18

ns

2

6

SYSCLK frequency stability

—

1000

ppm

7

SYSCLK jitter

—

±150

ps

3

8

MPC105 internal PLL relock time

—

100

µs4

9

Phase-lock loop VCO operating range

120

200

MHz

5

Notes:

1. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.

2. Specification value is at maximum frequency of operation.

3. Cycle-to-Cycle Jitter

4. Relock timing is guaranteed by design and is not tested.

5. For configuration of the VCO, see Table 10.

5a

5b

VM

VM = Midpoint Voltage (1.4 V)

2

3

CVIL

CVIH

1

SYSCLK

VM

VM

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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