105 Hardware Specifications

21

Preliminary/Subject to Change without Notice

Figure 12. PLL Power Supply Filter Circuit

1.6.3 Decoupling Recommendations

The MPC105 can generate transient power surges and high frequency noise in its power supply, especially

while driving large capacitive loads. This noise must be prevented from reaching other components in the

MPC105 system, and the MPC105 itself requires a clean, tightly regulated source of power. Therefore, it is

recommended that the system designer place a decoupling capacitor with a low ESR (effective series

resistance) rating to at least one Vdd pin of the MPC105.

This capacitor should be at least 0.1

µF to provide both high and low frequency filtering, and should be

placed as close as possible to their associated Vdd pin. Surface-mount tantulum or ceramic devices are

preferred. It is also recommended that these decoupling capacitors receive their power from Vdd and GND

power planes in the PCB, utilizing short traces to minimize inductance in the traces. Power and ground

connections must be made to all external Vdd and GND pins of the MPC105.

1.6.4 Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal

level. Unused active-low inputs should be connected to Vdd. Unused active-high inputs should be

connected to GND.

Note that in 32-bit data bus mode, the unused processor bus data signals (DL0-DL31) must be connected to

pull-up resistors for proper device operation.

1.6.5 MPC105 Thermal Management Information

The use of C4 die on a CBGA interconnect technology offers significant reduction in both the signal delay

and the microelectronic packaging volume. Figure 13 shows the salient features of the C4/CBGA

interconnect technology. The C4 interconnection provides both the electrical and the mechanical

connections for the die to the ceramic substrate. After the C4 solder bump is reflowed, epoxy (encapsulant)

is under-filled between the die and the substrate. Under-fill material is commonly used on large high-power

die; however, this is not a requirement of the C4 technology. The package substrate is a 21 mm multilayer-

cofired ceramic. The package-to-board interconnection is by an array of orthogonal 90/10 (lead/tin) solder

balls on 1.27 mm pitch. During assembly of the C4/CBGA package to the board, the high-melt balls do not

collapse.

Figure 13. Exploded Cross-Sectional View

Vdd

AVdd

10 Ohms

10 uF

0

.1 uF

GND

Chip with C4 Encapsulant

Ceramic Substrate

CBGA Joint

Printed-Circuit Board

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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